Abstract: An operational amplifier circuit which is substantially insensitive to inherent parasitic capacitance associated therewith is provided. An error voltage resulting from the parasitic capacitance is typically coupled onto a capacitor which is connected to a first input of an operational amplifier. To compensate for the error voltage, a substantially identical second error voltage is created and coupled to a second input of the operational amplifier, thereby cancelling the effects of the first error voltage.

Abstract: A high voltage circuit provides a high voltage signal output in response to receiving a logic signal. The high voltage circuit includes a regenerative circuit which is coupled to a high voltage terminal and a 5 volt power supply terminal. An inverting push-pull buffer responsive to the logic signal provides a signal which is regenerated to the high voltage by the regenerative circuit when the logic signal is in a first state and maintains the signal at ground potential when the logic signal is in a second logic state.

Abstract: A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.

Abstract: A fast carry propagate adder circuit which differentially senses a carry input bit with a sense amplifier is provided. First and second carry bit conductors are precharged to an equal voltage potential by a precharge portion. A voltage differential between the two carry bit conductors is sensed to provide both an output sum bit and an output carry bit in response to two input sum bits, an input carry bit and the complement of the input carry bit.

Abstract: A circuit uses a pair of transistors in series to provide an output pulse which indicates an address transition has occurred. A duration of joint conductivity of the pair of transistors determines the duration of the output pulse. For an address transition, one of the transistors is rapidly turned on while the other is slowly turned off with a slow fall time. The fall time is adjustable to achieve an adjustable duration of joint conductivity, and thereby an adjustable output pulse width.

Abstract: A virtual ground memory which has four state cells coupled to bit lines has a load directly connected to each bit line to reduce the degradation of the output of a selected memory cell due to voltage drop caused by current flow between load and selected memory cell. Additionally, loads which are coupled to the bit lines are also coupled to an adjacent virtual ground line to avoid providing a separate power supply line for the loads.

Abstract: A power multiplexer switch for alternatively coupling a supply or standby voltage line to an output voltage line comprises a first switching means for coupling an intermediate node to a common voltage line. Second switching means are responsive to the first switching means for coupling the supply voltage line to the output voltage line. Third and fourth series switching means connected to the intermediate node couple the standby voltage line to the output voltage line when a voltage on the standby voltage line exceeds that on the supply voltage line.

Abstract: A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second differential amplifier coupled to the pair of bit lines which is enabled a predetermined time duration following the occurrence of the first signal.

Abstract: A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an externally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.

Abstract: An oscillator with inverter and delay stages is coupled between first and second reference terminals. In one aspect a depletion transistor is connected between a power supply terminal and the first reference terminal to provide a reference voltage thereat. In another aspect the delay stages each have a control terminal for controlling the delay thereof. A temperature compensation circuit has a control transistor which provides a voltage to the control terminals of the delay stages which is inversely proportional to the threshold voltage of the control transistor.

Abstract: An analog switch structure which utilizes three switches and has low leakage current is provided. A first switch couples an input terminal to a node in response to a control signal. A second switch connects the node to an output terminal in response to the control signal. A buffer circuit is connected to the output terminal for providing a buffered output signal. A third switch is connected between the buffered output signal and the node to selectively connect the buffered output signal to the node, thereby maintaining zero voltage potential across the second switch.

Abstract: A heat spreader which is self-positioning into a mold cavity prior to encapsulation in plastic is provided. To minimize capacitance between the spreader and a metal lead frame having a semiconductor die mounted thereon, the heat spreader has a frame with notches in the opposite ends which define bifurcated limbs. Lateral standoffs extend from each of the sides thereof and feet extend from the bottom surface thereof. A central portion extends a predetermined distance from the top surface thereof for intimate positioning with the lead frame. The standoffs, limbs and feet are sized to firmly position the heat spreader upon insertion into the mold cavity. To maintain substantially constant capacitance between the spreader and the lead frame from part to part, each bifurcated limb has an inner edge which complements or conforms to the portion of the lead frame which will overlay the limb in the encapsulated plastic.

Abstract: A CMOS Schmitt trigger which has two series-connected inverters uses both an input and an output signal to provide hysteresis. A pair of series-coupled transistors is coupled between a power supply terminal and a node between the two inverters. One of the transistors has a control electrode for receiving the input signal. The other of the transistors has a control electrode for receiving the output signal.

Abstract: An error checking and correcting (ECC) system implemented in large scale integration (LSI) form having a predetermined Hamming code checks the accuracy of data and corrects the data via check bits. A method and apparatus for translating the predetermined Hamming code to an expanded class of Hamming codes is disclosed.

Abstract: A circuit is provided in MOS technology which replaces a defective row of memory cells with a redundant row of memory cells in response to the address of the defective row and an implementation signal. The defective row is disabled by a floating gate fusible link which responds to the output of the decoder of the defective row as driven by the address thereof and to the implementation signal. The redundant row is implemented by floating gate fusible links which disable the inputs of the decoder of the redundant row which correspond to complements of the address in response to the address and the implementation signal. The implemented redundant row then receives address signals without any additional propagation delays.

Abstract: An on chip voltage monitor is provided for an integrated circuit having an analog to digital converter. In one form, the threshold voltage of a plurality of diode-connected test transistors is monitored by selectively positioning the transistors on an integrated circuit die. For each test transistor, a current source in response to a control circuit is selectively coupled thereto for sourcing predetermined amounts of current. The analog to digital converter in response to the control circuit is selectively coupled to the test transistor to measure the voltage across the test transistor. From this data, an accurate approximation of the threshold voltage may be made. Other voltages which are not easily externally measureable may be coupled to the on chip digital to analog converter for easy and accurate measurement.

Abstract: A frequency generator circuit which provides an output signal which is both synchronous with and proportional in frequency to a clock signal of predetermined frequency in response to an input control signal is provided. A frequency divider portion couples a clock signal of divided frequencies to predetermined control electrodes of series-connected switches which selectively couple an output node to a reference voltage node. A decode portion selectively bypasses predetermined switches in response to the input control signal to selectively couple the reference node to the output node. A latch is coupled to the output node to hold the decoded output signal at a predetermined logic level for a predetermined amount of time.

Abstract: An n-bit adder circuit, where n is an integer, for providing carry select addition of two input numbers is provided. A rank ordered plurality of section adders each have a plurality of full adders. Each full adder utilizes a single half adder to provide two sum bits which are coupled to a multiplexer which is an integral part of each section adder. One sum is for a carry-in and the other sum is for no carry-in. A method of minimizing logic circuitry which provides carry bits and carry sum select bits is provided. The carry bits and carry sum select bits control which of the two sums are provided by each section adder. By providing the carry bits and carry sum select bits in complement form every other order of section adder, logic circuitry and logic gate delays are minimized.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Abstract: A switched capacitor comparator having two or more stages of differential input operational amplifiers utilizing sequentially switched feedback portions and feedback capacitors is provided. The use of feedback capacitors in a sequentially switched comparator provides accurate gain and stability. To further reduce offset voltage errors, a solid state transmission gate having a low "on" resistance is disclosed. A transmission gate having capacitors for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate is provided to compensate parasitic capacitance effects. When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.