Patents Represented by Attorney, Agent or Law Firm Jeffrey Van Myers
  • Patent number: 4680760
    Abstract: Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Jesse R. Wilson, Terry V. Hulett
  • Patent number: 4680086
    Abstract: A method for etching multi-layer structures particularly suited for patterning refractory metal silicide/polysilicon sandwiches. A first dry etch process is carried out in a first dry etch chamber and is selected to rapidly and anisotropically etch the uppermost layer, typically a refractory metal silicide. A second dry etch process is carried out in a second etch chamber and is selected to rapidly and anisotropically etch the underlying layer, typically polysilicon, while having a high selectivity to any material underlying the underlying layer. The first process is preferably a fluorine-chemistry process with low frequency RF energy and the substrate resting on the grounded electrode. The second process is preferrably a chlorine-chemistry process with high frequency RF energy and the substrate resting on the powered electrode.
    Type: Grant
    Filed: March 20, 1986
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Patrick K. Thomas, Dennis C. Hartman, Jasper W. Dockrey
  • Patent number: 4680471
    Abstract: An integrated circuit comprising: a semiconductor die having an integrated circuit formed therein; a package for supporting the die and for providing electrical contact thereto, the radiation properties of the package having been characterized as follows: fabricating a detector using a semiconductor fabrication technique, the detector having substantially the same dimensions as an integrated circuit to be packaged in the packaging materia; packaging the detector using integrated circuit packaging techniques; and measuring the radiation environment of the detector.
    Type: Grant
    Filed: March 20, 1985
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Steven L. Morris, Gary C. Lewis
  • Patent number: 4679194
    Abstract: In a data processor having an instruction which requires the loading of the contents of two (2) successive locations in the address space during respective bus cycles, test circuitry is provided to selectively force the processor to twice load the contents of the same location upon execution of the instruction. Using this special load double test instruction, the processor is able to detect more precisely when the contents of the memory location changes in value as a result of the activity of other circuitry.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: July 7, 1987
    Assignee: Motorola, Inc.
    Inventors: Tulley M. Peters, William C. Bruce, Jr.
  • Patent number: 4673443
    Abstract: A continuous ionizer adapted to introduce selected ions into a continually flowing stream of liquid. To ensure that a maximum concentration of ions is incorporated, the continuous ionizer is configured so that turbulent and intimate mixing of the ionizing gas and liquid to be ionized occurs. The flow of ionizing gas is regulated by a liquid level sensor to prevent a gas/liquid mixture from proceeding downstream from the ionizer. The apparatus and method of this invention are particularly suited to situations where deionized water is used in a process which causes undesired static electricity discharges, and clean, ion-possessing water is preferred, such as semiconductor processing.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: June 16, 1987
    Assignee: Motorola, Inc.
    Inventor: Allan M. Fetty
  • Patent number: 4672610
    Abstract: A built in self test input generator (BISTIG) for programmable logic arrays (PLAs) providing exhaustive fault coverage, but requiring additional space of only 8 to 15% of the PLA area. The BISTIG contains a test vector generator and a product term control, each of which has a sequence generator and associated decoder. The sequence generators generate log.sub.2 (N) and log.sub.2 (M) test vectors for the test vector generator and the product term control respectively, where N is the number of inputs to the PLA and M is the number of product terms connecting the first level of the PLA with the second level of the PLA.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: June 9, 1987
    Assignee: Motorola, Inc.
    Inventor: John E. Salick
  • Patent number: 4672421
    Abstract: A mounting means for a semiconductor integrated circuit, the mounting means comprising a semiconductor material having a mounting surface as one major surface thereof, a semiconductor integrated circuit mounted on the major surface of the semiconductor material, and means for electrically connecting the integrated circuit to the semiconductor material. The mounting means has a coefficient of thermal expansion similar to the semiconductor integrated circuit mounted thereon.
    Type: Grant
    Filed: May 15, 1986
    Date of Patent: June 9, 1987
    Assignee: Motorola, Inc.
    Inventor: Paul T. Lin
  • Patent number: 4669059
    Abstract: A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The method and circuit allows the code to be stored in the control register once and only once between system resets.
    Type: Grant
    Filed: November 7, 1983
    Date of Patent: May 26, 1987
    Assignee: Motorola, Inc.
    Inventors: Wendell L. Little, Kenneth R. Burch
  • Patent number: 4662956
    Abstract: A method for the prevention of dopant diffusion from the back side of a doped semiconductor substrate during epitaxial layer growth. The entire surface of the substrate is first covered with a cleanly etchable material. Around the entire first layer is formed a second dopant diffusion barrier layer. The front sides of the layers are then selectively etched away to expose the front side of the substrate upon which the epitaxial layer will be grown without contamination of dopant diffusion from the sealed back side of the substrate.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: May 5, 1987
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, Joe Steinberg, H. Scott Morgan
  • Patent number: 4663545
    Abstract: A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.
    Type: Grant
    Filed: November 15, 1984
    Date of Patent: May 5, 1987
    Assignee: Motorola, Inc.
    Inventors: Joseph Pumo, William D. Atwell, Jr., Doyle V. McAlister
  • Patent number: 4663546
    Abstract: A two stage synchronizer circuit for synchronizing an asynchronous input signal with a local clock signal includes a reference inverter for generating a reference signal, a first sense amplifier for amplifying the difference between the reference signal and the asynchronous input signal, buffer inverters coupled to the output on the sense amplifier, a second sense amplifier coupled to the output of the buffer inverters, and an output inverter for delivering the desired synchronized signal. The reference inverter and the first and second buffer inverters have the same switch point so as to substantially reduce the probability of the generation of a meta-stable output. Furthermore, the first and second sense amplifiers and output inverter also have the same switch point as the reference inverter.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: May 5, 1987
    Assignee: Motorola, Inc.
    Inventors: John K. Eitrheim, Bernard J. Pappert, Ashok H. Someshwar
  • Patent number: 4661192
    Abstract: A low cost process for bonding a plurality of integrated circuit die to a variety of die support frames using existing, readily available equipment. Tape automatic bonding (TAB) processes offer a number of new possibilities in the assembly and packaging of integrated circuits. However, the investigation of TAB techniques or the use of TAB techniques on low volume parts is prohibited by the high cost of "bumping" or putting interconnection balls on the chip or the tape leads. The process permits placing balls on the bonding pads of a plurality of die by a wire bonder, cutting off the wire, planarizing the balls, coating the planarized region with a conductive epoxy and then registering and bonding the die to corresponding conductive patterns on die support frames.
    Type: Grant
    Filed: August 22, 1985
    Date of Patent: April 28, 1987
    Assignee: Motorola, Inc.
    Inventor: Michael B. McShane
  • Patent number: 4661724
    Abstract: A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver circuits receive a decoded address signal which corresponds to that particular driver circuit, each have an output coupled to a corresponding word line, and each have an input which, when at a logic high, causes that word line driver to couple its corresponding decoded address signal to its corresponding word line. The first coupling circuit couples the output of the logic decoder to the input of only the driver circuit which corresponds to an active decoded address signal during the active cycle, and for coupling the output of the logic decoder to all of the driver circuits in the inactive cycle.
    Type: Grant
    Filed: May 6, 1985
    Date of Patent: April 28, 1987
    Assignee: Motorola, Inc.
    Inventors: Scott Remington, William L. Martino, Jr.
  • Patent number: 4661931
    Abstract: A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: April 28, 1987
    Assignee: Motorola, Inc.
    Inventors: Stephen T. Flannagan, Paul A. Reed
  • Patent number: 4661887
    Abstract: An integrated circuit package having a plurality of leads capable of holding a quantity of solder paste prior to bonding to a printed circuit board or other substrate. The solder paste bearing structure may be straight or spiral grooves, or even a slot or roughened surface, running down at least the lower length of the leads as long as some mechanism is present which will first hold the solder paste or other electrically conductive binder on the lead and then deliver the binder to the end of the lead to produce an electrical and structural bond in a binder flowing operation. Application of the solder paste to the leads is accomplished by simply dipping the package leads into the paste thereby eliminating the need to make a solder mask for the substrate as well as the task of aligning the mask to the substrate.
    Type: Grant
    Filed: October 31, 1985
    Date of Patent: April 28, 1987
    Assignee: Motorola, Inc.
    Inventor: Paul T. Lin
  • Patent number: 4659944
    Abstract: A voltage detecting circuit is provided for generating an output signal when an input signal exceeds the power supply voltage by a predetermined amount. A reference current is established by an output stage using a first current mirror. A second current mirror is connected to the output stage and detects the input voltage level by forcing a greater or lesser amount of current through the output stage to provide a high or low level output voltage.
    Type: Grant
    Filed: April 8, 1985
    Date of Patent: April 21, 1987
    Assignee: Motorola, Inc.
    Inventors: James A. Miller, Sr., Robert N. Allgood, Richard W. Ulmer
  • Patent number: 4658381
    Abstract: A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the bit lines to develop a voltage differential. In response to a change in the row address the bit lines are equalized and precharged. In response to a change in the column address, the bit lines are precharged without being equalized so that the developed voltage differential on the bit lines is maintained.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: April 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Paul A. Reed, Stephen T. Flannagan
  • Patent number: 4652997
    Abstract: A data processing system having apparatus for selectively executing nested do loops with minimum overhead is provided. The apparatus may be added to a system which executes do loops. The method of execution of the do loops may be any of a myriad of conventional methods. Memory storage is provided for storing the number of iterations remaining in a do loop and an active loop flag. The active loop flag indicates that a do loop is active and enables the do loop apparatus. The active loop flag also indicates whether the data stored in memory is associated with an active loop. New parameters relating to the nested do loop may be used by the same circuitry which executes the do loop thereby eliminating duplication of circuitry. Upon termination of the nested do loop, the memory storage restores the information required to complete the do loop by the apparatus.
    Type: Grant
    Filed: November 27, 1985
    Date of Patent: March 24, 1987
    Assignee: Motorola, Inc.
    Inventor: Kevin L. Kloker
  • Patent number: 4649476
    Abstract: In a microcomputer, an address mapper allows the user to selectively map a resource which is ordinarily addressable in one portion of the address range of the microcomputer into a correspondingly sized area elsewhere in the address range. Using a resource map address stored by the user in an addressable map register, the mapper continuously compares the map address to a corresponding number of bits on the microcomputer's address bus. When a match is detected, the mapper enables the address decoder of the mapped resource. The mapper can also map the map register. Since the mapper can map more than one resource, an interlock mechanism resolves access conflicts.
    Type: Grant
    Filed: October 31, 1983
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventor: James M. Sibigtroth
  • Patent number: 4649477
    Abstract: A data processor having size selector in a controller for explicitly selecting the size of an operand independent of an instruction in an instruction register, together with means for selectively enabling the instruction register or other functional block, or a size selector to select the size of the operand. A size bus and a size multiplexer are also provided to route the size instructions. By using this size mechanism, the amount of sequencing and control logic is significantly reduced from prior data processors. The mechanism allows operations of different sizes to be performed during a single instruction while allowing instruction dependent sizing to be done residually.
    Type: Grant
    Filed: June 27, 1985
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventors: Douglas B. MacGregor, William C. Moyer