Patents Represented by Attorney, Agent or Law Firm Jeffrey Van Myers
  • Register circuit for transmitting and receiving serial data
    Patent number: 4648105
    Abstract: A register circuit for serial transmission or reception of digital data in a microprocessor controlled system is provided. A first plurality of rank ordered latches is provided to receive in parallel data to be transmitted. A second plurality of rank ordered latches is provided wherein each of the second plurality of latches except the highest ranked latch interconnects the first plurality of latches. The first and second plurality of latches function together to serially clock output data to be transmitted. The two pluralities of latches form a single register circuit which also serially receives data and latches the received data in response to a control circuit implemented as a "walking one" register. After the serially received data is latched, the data is provided for use by the microprocessor controlled system in parallel output form.
    Type: Grant
    Filed: June 6, 1985
    Date of Patent: March 3, 1987
    Assignee: Motorola, Inc.
    Inventors: Gordon W. Priebe, Arthur D. Collard
  • N-bit magnitude comparator
    Patent number: 4648059
    Abstract: A circuit for selectively determining whether a first number is greater than or equal to or less than or equal to a second number, comprising a means for adding a first number and a complementary function of a second number, and logic means for generating a signal for carry-in and for combination with a carry-out of the means for adding for producing a signal indicative of whether the second number is within the parameters established by the first number and the carry-in.
    Type: Grant
    Filed: September 13, 1984
    Date of Patent: March 3, 1987
    Assignee: Motorola, Inc.
    Inventor: Arthur J. Gregorcyk
  • Parasitic insensitive switched capacitor input structure for a fully differential operational amplifier
    Patent number: 4647865
    Abstract: An input structure which is parasitic insensitive and allows a fully differential amplifier to receive a single input voltage while maintaining a predetermined common-mode input voltage is provided. A single input voltage is charged onto two capacitors which are coupled in series between the input voltage and a predetermined common-mode reference voltage terminal during a first time period. During a second time period, the two capacitors are reconfigured so that each capacitor is connected between the reference voltage terminal and a predetermined one of the inputs of the fully differential amplifier. Due to the balanced nature of the input structure, all parasitic capacitance error terms are rejected by the differential amplifier.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: March 3, 1987
    Assignee: Motorola, Inc.
    Inventor: Alan L. Westwick
  • Reduced power sense amplifier
    Patent number: 4644197
    Abstract: A sense amplifier has a pair of differential amplifiers and a pair of current mirrors. Each of the current mirrors has a master and a slave. The slaves are used for both loads of one of the differential amplifiers, and the masters are used for both loads of the other of the differential amplifiers. The pair of current mirrors are formed of transistors of one conductivity type while the differential amplifiers are formed of transistors of another conductivity type.
    Type: Grant
    Filed: January 28, 1985
    Date of Patent: February 17, 1987
    Assignee: Motorola, Inc.
    Inventor: Stephen T. Flannagan
  • Tri-state differential amplifier
    Patent number: 4644196
    Abstract: An amplifier has a pair of common source transistors in which the sources are coupled together during a first mode of operation and isolated from each other during a second mode of operation. A current source provides current between a power supply terminal and these sources during the first mode and prevents current flow therebetween during the second mode. A pair of switchable loads act as loads for the common source transistors during the first mode and are switched off during the second mode.
    Type: Grant
    Filed: January 28, 1985
    Date of Patent: February 17, 1987
    Assignee: Motorola, Inc.
    Inventor: Stephen T. Flannagan
  • Orientation of reference cells in a memory
    Patent number: 4636979
    Abstract: A memory which has memory cells with first and second orientations also has reference cells with first and second orientations. When a memory cell with the first orientation is selected, an output of a reference cell with the first orientation is compared to that of the selected cell with the first orientation. When a memory cell with the second orientation is selected, an output of a reference cell with the second orientation is compared to that of the selected cell with the second orientation.
    Type: Grant
    Filed: November 2, 1984
    Date of Patent: January 13, 1987
    Assignee: Motorola, Inc.
    Inventor: William J. Donoghue
  • Summation of address transition signals
    Patent number: 4636991
    Abstract: A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
    Type: Grant
    Filed: August 16, 1985
    Date of Patent: January 13, 1987
    Assignee: Motorola, Inc.
    Inventors: Stephen T. Flannagan, Paul A. Reed
  • Electronic switch for digital telephone
    Patent number: 4636587
    Abstract: An electronic switch for supplying power to a digital telephone which consumes substantially no power in the idle mode. A transistor for supplying power to the digital telephone is latched on in either of two situations. In the first situation, the telephone's hookswitch is closed. A second transistor turns on and maintains the first transistor on even after the hookswitch has been opened. In the second situation, a voltage pulse is applied to the input voltage conductor lines causing the first and second transistors to turn on. Again, the second transistor maintains the first transistor on. The circuit is inactivated by a sleep signal which turns off the second transistor which in turn turns off the first.
    Type: Grant
    Filed: September 16, 1985
    Date of Patent: January 13, 1987
    Assignee: Motorola, Inc.
    Inventor: Glen J. Zoerner
  • Parasitic compensated switched capacitor integrator
    Patent number: 4636738
    Abstract: A switched capacitor integrator for receiving a single input signal is compensated for parasitic capacitance errors with a minimum amount of circuitry. Although a single-ended amplifier is provided, a differential amplifier input is used which receives equal amounts of parasitic charge to effectively cancel charge errors. The size of the compensating capacitive circuitry may be reduced by making the input parasitic capacitance at one of the inputs proportionately larger so that the noise gain in both positive and negative signal paths remains substantially the same.
    Type: Grant
    Filed: February 3, 1986
    Date of Patent: January 13, 1987
    Assignee: Motorola, Inc.
    Inventors: Alan L. Westwick, Roger A. Whatley
  • Circuit for selectively extending a cycle of a clock signal
    Patent number: 4636656
    Abstract: A circuit comprising first, second and third latches selectively extends a cycle of a clock signal of a memory system in response to a control signal. A second clock signal having a frequency which is a predetermined multiple of the clock signal of the memory system is coupled to an input of the second and third latches. The first latch receives first and second control signals indicating the detection of parity errors in the memory system and suspends or delays the normal transition of the third latch which provides the memory system clock signal, thereby extending a cycle of the clock signal. The second latch resets the first latch which thereafter resets the third latch causing the clock signal to return to normal cycle operation.
    Type: Grant
    Filed: May 21, 1984
    Date of Patent: January 13, 1987
    Assignee: Motorola, Inc.
    Inventors: Ralph E. Snowden, Robert D. Whitley
  • Data processor having selective breakpoint capability with minimal overhead
    Patent number: 4635193
    Abstract: A data processor communicates with a peripheral device and selectively sets breakpoints with minimal overhead. The data processor utilizes an instruction register to store instructions to be executed. Control means communicate with the peripheral device to selectively set a breakpoint in a software program. When repetitions of the breakpoint are encountered, an exception handler is only executed at the desired breakpoint to minimize overhead. A control portion of the processor selectively receives a breakpoint instruction and stores the breakpoint instruction in the instruction register.
    Type: Grant
    Filed: May 13, 1986
    Date of Patent: January 6, 1987
    Assignee: Motorola, Inc.
    Inventors: William C. Moyer, John E. Zolnowsky, David S. Mothersole
  • Power-on-reset circuit having a differential comparator with intrinsic offset voltage
    Patent number: 4634905
    Abstract: A power-on-reset circuit which functions with variations in process, temperature and supply voltage is provided. A differential comparator structure is provided which utilizes a differential pair of transistors and which has a substantially constant intrinsic offset voltage associated therewith. The intrinsic offset voltage is created by making one of the transistors of the differential pair of lightly doped depletion device and the other transistor a heavily doped depletion device. A second reference voltage is provided in response to a detected power-up voltage and is implemented with a voltage divider. Power-on-reset is provided in response to the relationship of the levels of the first and second reference voltages.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: January 6, 1987
    Assignee: Motorola, Inc.
    Inventor: Jules D. Campbell, Jr.
  • Partial memory selection using a programmable decoder
    Patent number: 4633429
    Abstract: A technique for providing a partial memory of one half of the possible storage bits comprised of any two quadrants is implemented by decoupling the one of four decoder used for normal operation and providing a programmable decoder which is capable of being programmed to select one of any two quadrants. If only one quadrant is to form the partial memory, the programmable decoder can be programmed to select only one latch. In another embodiment, a decoder is provided which can also be programmed to select one of any three quadrants.
    Type: Grant
    Filed: December 27, 1982
    Date of Patent: December 30, 1986
    Assignee: Motorola, Inc.
    Inventors: Alan J. Lewandowski, Jerry D. Moench
  • Data processor having dynamic bus sizing
    Patent number: 4633437
    Abstract: In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port.
    Type: Grant
    Filed: June 26, 1984
    Date of Patent: December 30, 1986
    Assignee: Motorola, Inc.
    Inventors: David S. Mothersole, Lester M. Crudele, James L. Tietjen, Robert R. Thompson
  • Clock monitor circuit and method
    Patent number: 4633097
    Abstract: A clock monitor circuit and method for providing an indication at the output thereof of the presence of an input clocking signal. If the clock input is operating properly, two charge storage nodes will be charged and the output of the circuit will be high. If the clock input is stuck, the output of the clock monitor circuit will be low.
    Type: Grant
    Filed: November 17, 1983
    Date of Patent: December 30, 1986
    Assignee: Motorola, Inc.
    Inventor: B. Chris Dewitt
  • Heat exchange apparatus for high temperature LPCVD equipment
    Patent number: 4630669
    Abstract: A heat exchanger apparatus having two sleeves which fit together to seal a sinuous heat exchange fluid channel between them where the channel is open along its length prior to assembly. The sleeves may be made removable to permit easy cleaning of the heat exchange fluid channel. The heat exchange fluid channel may thus be directly cleaned along its entire length in contrast to conventional heat exchangers employing tubes, where the tube interior can be accessed only from the ends. In one embodiment, the channel has a rectangular cross-section to enhance the heat exchange capability of the apparatus.
    Type: Grant
    Filed: August 15, 1985
    Date of Patent: December 23, 1986
    Assignee: Motorola, Inc.
    Inventors: Peter H. Kessler, Wilson D. Calvert, Sr., Faivel S. Pintchovski
  • Chip select speed-up circuit for a memory
    Patent number: 4630239
    Abstract: A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to the select mode, these appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such false transition as an actual transition, the detection of address transitions is suppressed for a predetermined delay time following the transition from the select to deselect modes.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: December 16, 1986
    Assignee: Motorola, Inc.
    Inventors: Paul A. Reed, Stephen T. Flannagan
  • Clock signal test circuit
    Patent number: 4628253
    Abstract: An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled upon receiving its associated clock signal. Consequently, the current sources are sequentially enabled until a clock signal fails to occur at which time no more clock signals occur so that no more current sources are enabled. The current sources are connected to a probe pad which is accessible external to the integrated circuit. Test apparatus for detecting the enabled current sources can be connected to the integrated circuit at the probe pad.
    Type: Grant
    Filed: March 30, 1984
    Date of Patent: December 9, 1986
    Assignee: Motorola, Inc.
    Inventors: Ruey J. Yu, William L. Martino, Jr.
  • Slew rate limited driver circuit which minimizes crossover distortion
    Patent number: 4622482
    Abstract: A driver circuit which provides an output voltage which is slew rate limited substantially independent of the value of any load which may be coupled thereto is provided. A pair of transistors of opposite conductivity type operate in push-pull fashion to drive the output voltage in response to a control signal. Capacitors are utilized to perform slew rate limiting. Additionally, each of the transistors is selectively dynamically biased to insure a substantially linear slew rate.
    Type: Grant
    Filed: August 30, 1985
    Date of Patent: November 11, 1986
    Assignee: Motorola, Inc.
    Inventor: Jeffrey D. Ganger
  • Clean room hood
    Patent number: D288732
    Type: Grant
    Filed: October 24, 1983
    Date of Patent: March 10, 1987
    Assignee: Motorola, Inc.
    Inventors: Teresa L. Widener, Richard L. Prilliman, James B. Wilhelm, Jr., Donna A. Barger, Valerie J. Trombley