Abstract: A roadway vehicle sensor includes a coextrusion having a linear conductive section and a linear non-conductive section forming a vehicle deformable closed housing. The linear conductive section has an inwardly projecting conductive plunger along the length thereof which is fused to wedge removal arms. The linear non-conductive section has a pair of inwardly projecting insulating wings having wing tips spaced apart a distance defining a plunger gap. The insulating wings also define a contact chamber into which the plunger protrudes only upon deformation of the vehicle deformable housing by a vehicle. Preferably, the vehicle deformable housing has a flat side on the exterior for engagement with a roadway surface. A contact assembly in the contact chamber has one or more flat conductive lane switch segment, each flat conductor lane switch segment having a width which avoids phantom switch closures.

Abstract: A printed circuit board having micro-vias used to connect a portion of the contacts in a selected row or column to the first internal layer of the board, thereby creating routing channels on the second and subsequent internal layers of the board between selected rows or columns of through-board vias used to connect the remaining contacts and a BGA package adapted to be used with the printed circuit board.

Abstract: Techniques for bandwidth management and flow control on a resilient packet ring (RPR) network is described. The RPR requires allocation and guarantee of a bandwidth for each channel between two nodes on the ring. The bandwidth is managed by shaping traffic on a channel at the source by using a bandwidth allocation factor calculated at each node. The bandwidth allocation factor, which is communicated to other nodes, is calculated by using a recursive nonlinear function of the transit buffer size.

Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.

Abstract: In a multi-service network, layer 2 traffic such as IP traffic according to the invention is carried over ATM SVCs or SPVCs. Methods of setting up such connections using the PNNI protocol are also discussed. Using enhancements to the standard ATM SPVC/SVC signaling messages, layer 3 IP routing processes on multi-services switches on opposite ends of the network allow traffic to flow transparently through an underlying layer 2 virtual connection. This provides a simple and efficient way to transport IP packets across an ATM network.

Abstract: Whenever a DSLAM or a network node receives a Group Join message, it compares the MAC address of the originating STB to that of previous Join messages with their existing connections. If a match is found, then the DSLAM will initiate a GSQ for the group of the matching previous Join request. If there is not enough resources to satisfy the requirements of Group Join messages, then it may either be ignored, or queued for later processing, once the normal GSQ sequence is complete and resources are available. If the multicast group is no longer needed, the connection to the group is then terminated, as per normal GSQ processing. This frees up bandwidth for any new Join messages. The normal GSQ processing clears the trouble caused by the loss of Leave Message.

Abstract: A fresh masonry wall protection device and method for rapidly protecting a newly laid block or brick wall from inclement weather. A thin plastic channel element has a top panel member and a pair of parallel side panel members. The top panel member has a smooth, flat inner face which is adapted to engage the topmost surface of the newly laid block or brick wall. The parallel side panel members are springy and angled inwardly so that they engage the newly laid block or brick wall and have lower ends which angle outwardly to form a water deflector and guideway for installing the protection device on the newly laid block or brick wall. The top panel member is provided with a plurality of spaced rebar punchouts. One end of the channel element is provided with guide lines for adapting the ends to cover corners and other wall angulations.

Abstract: A center of gravity (C/G) control system for a vehicle includes sensors to measure the center of gravity shift and mass shift of the human body in relation to the vehicle, a controller to determine outputs, a dynamically adjustable vehicle system, and a power supply. The sensor measures the direction and rate of shift of the center of gravity and mass shift of the human and creates a representative input signal. The controller determines the appropriate outputs in response to the relative center of gravity shift data received. The dynamically adjustable vehicle system receives the controller output and performs the expected action.

Abstract: A method and associated device for selecting one of a number of equivalent paths in forwarding a network message from a node of a communication network. A source and destination address is provided for the network message. The addresses are formed of individual bit values, and these values have a relative mapping between them. The relative mapping is decorrelated to obtain a decorrelated address pair. A randomized selection function is applied to the decorrelated address pair to produce an index which is derived from the relative sequence of bit values of the decorrelated address paid. The index is then used to select one of the equivalent paths. The associated device provides an address reader, a decorrelation module and a randomized selection module for performing the method previously described.

Abstract: A method for optimizing area array device pin utilization and reducing the number of layers on a multilayered PCB comprising: preparing a package of BGA pin-out maps which anticipate the effect of existing fixed pins and derives the resulting optimum pin location assignment. Each pin-out map includes an indication of the best routing for circuits from a given component to be mounted to a PCB. Applying the package of pin-out maps during an area array pin assignment phase, thereby making an area array package capable of supporting the optimum routing configuration proposed by the pin-out maps. Applying the package of pin-out maps during a PCB design phase so that the optimum circuit routing to each pin is achieved, thereby completing the strategy layed out by the proposed pin-out maps, resulting in a lower number of PCB layers.

Abstract: The backpressure flow control mechanism is widely used in telecommunications network. Actions of the flow control scheme are not instantaneous in that latency always exists between action and reaction, resulting in a flow control round trip time. This flow control round trip time causes ambiguity in determining the amount of traffic in transit. The invention monitors the amount of traffic which is on the way toward the queue during the past period of the round trip time, thus eliminating the ambiguity. A more precise control of traffic flow is possible, realizing reduction of storage space in the queue by one half. In one embodiment, the invention keeps a historical record of flow control signals sent back during the most recent flow control round trip time.

Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Abstract: A method and apparatus of communicating data packets across the midplane of an electronic system in which the packets are partitioned into segments of a predetermined size and then serialized to a predetermined width. The serialized packets are transmitted, in phase staggered segments, across the midplane on a respective channel, received into receiving end and the serialized segments that have traversed the midplane, are deserialized and reassembled into the original data packet.

Abstract: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, elongating and/or truncating the selected adjacent pairs and rotating their respective corresponding via pairs to adapt the spacing between the selected adjacent via pairs in the BGA land pattern and applying the capacitor pads to the selected via pairs. The selected adjacent via pairs and their respective link connectors are rotated, elongated and/or truncated in mutually opposite directions.

Abstract: A method and device for message discard of segmented message traffic in an aggregated message traffic stream of a communications network. The aggregated traffic stream has constituent traffic streams and each constituent traffic stream has segmented message traffic made up of formative segmented message units. An indication of whether a currently received segmented message unit of each constituent traffic stream is to be subjected to discard is stored in a memory. Upon each arrival of a segmented message unit, a detection is made by way of a reader as to whether a currently received segmented message unit denotes a delineation between two segmented messages. A determination of whether a current condition of traffic congestion exists is also made, and a processor utilizes the stored indication, the detection and the determination in arriving at whether a next to be received segmented message unit of the constituent message traffic stream is to be subjected to message discard.

Abstract: In many applications where it is desired to distribute a liquid onto a surface at a very small angle of incidence, it will be necessary to reduce the momentum of the droplets to prevent ricochet off the surface. Obvious methods such as using a restrictor, reducing the operating pressure, etc. are not satisfactory due to the inadequate flow, susceptibility to clogging, etc.

Abstract: Error correction on high speed interconnection links—backplane or extended wires (cable, optical fiber)—is exhaustively considered by many telecommunication vendors, especially those who offer “scalable router” products. Since the 64b/66b encoding scheme is a strong candidate of high speed interconnection protocol, error correction on 64b/66b encoded links is of interest. Although the IEEE 802.3 10G Ethernet standard does not specifically refer to packet loss, it can be shown that even only a single-bit error correction can significantly enhance the quality of the link. The present invention presents a simple and fast error-correction scheme that can be used in conjunction with the 64b/66b encoding in products where intra-board (chip-to-chip) or inter-shelf interconnections of high speed elements are required. It utilizes the CRC16 to optimize on error detection, correction, or both: it detects and corrects all single-bit errors and detects all multiple-bit errors.

Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Abstract: Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding vias in a row or column or selected consecutive rows or columns to achieve the enlarged spacing between rows or columns of vias in the BGA land pattern. Enhanced spacing between selected grid columns or rows of vias is provided such that some of the grid pitches for the vias are equal to that of the standard BGA and at least some are of a greater grid pitch.

Abstract: Methods and apparatus for controllably suppressing, at a network management system, SNMP event trap messages received from network nodes in a communications network are presented. The rate at which the traps are received from the network nodes is monitored and if the rate exceeds a threshold all subsequent traps received over a set time interval are not processed. The rate is calculated by counting received event traps over a time interval which is either preset or programmed. After the set time interval has passed all newly received traps are monitored. Information regarding traps received during the set time interval may be logged. Additionally, nodes from which excessive traps are received and indicating an event such as a Denial of Service (DoS) attack, are identified so that remedial action can be taken.