Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

Abstract: Systems and methods of mitigating DOS attacks on a victim node in a computer based communication system are presented. According to the methods a node such as a router upstream from the victim analyzes traffic flow directed to the victim node and if a pattern indicating a possible attack is detected a notification to the effect is sent to the victim node. The victim can either ignore the notification or chose to suggest or request attack mitigation measures be implemented by the upstream router. Alternatively the upstream router can implement attack mitigation measures without waiting for input from the victim node.

Abstract: A programmable configuration management infrastructure is provided. The programmable configuration management infrastructure employs Programmable Configuration Requests (PCRs) to perform configuration management over a definable target list of field-installed managed communication equipment subject to a definable schedule and configuration management policies. The programmable configuration management infrastructure provides for monitoring of configuration command execution and traps errors. In the event of detecting configuration command execution errors, the programmable configuration management infrastructure provides for restoring the configuration either for all targets processed or for the targets experiencing errors only as specified in the PCR definition. Recourse may be made to the validation of configuration change or configuration restoration commands as specified in the PCR definition.

Abstract: A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. Two or more compressors are separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.

Abstract: Method and apparatus for improving channel changing or channel surfing functionality in IGMP supported services.

Abstract: An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

Abstract: A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703, into a Sequential Circuit Model 705. The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707. The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates.

Abstract: A method and apparatus for conveying to a control shelf of a multi-shelf network node any master clock signal received via a plurality of interface cards associated with a plurality of peripheral shelves of the multi-shelf network node is presented. The apparatus operating in accordance with the method includes a peripheral shelf controller having: a selector selecting an External SYNChronization (ESYNC) signal from a multitude of ESYNC signals received at an associated peripheral shelf; a comparator deriving phase difference information in comparing the selected ESYNC signal and a SSYNC signal distributed by the control shelf; and encoder for digitally encoding the phase difference information at the peripheral shelf; means for conveying a digital phase difference information digitally between a peripheral shelf and the control shelf.

Abstract: A method for identifying service critical faults in a communications network and a network management system employing the method are provided. A service provisioning tool associated with the network management system and operating in accordance with the method, performs operations on a multitude of managed entity instances stored in a containment hierarchy associated with the network management system, the managed entity instances corresponding to managed field installed equipment. Received alarm information is used to ascribe operational states to corresponding managed entities in the containment hierarchy. Operating in accordance with the presented method, the service provisioning tool inspects low-level managed entities in the containment hierarchy and, if each managed entity of a group of low-level managed entities which provide a unitary function is “unavailable”, then the operational state of a corresponding high-level managed entity is set to the “unavailable” state.

Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Abstract: The invention provides a system and a method of electronically tracking a history of engineering change orders (ECOs) associated with a manufactured device. The device has at least one electronic component thereon. The method comprises, generally, storing in an electronic storage device associated with the device, the history of ECOs and updating the history of ECOs when a new ECO is associated with the device to indicate whether the new ECO was implemented on the device. The system utilizes the method and has an electronic storage device associated with the device and a data element stored therein. The contents thereof indicate the history of ECOs for the device and allow modification thereto to indicate whether a new ECO was implemented thereon. An ECO history enables a determination to be made of compatibilities between hardware and software elements and between hardware and firmware elements.

Abstract: A policing technique for a telecommunications traffic of variable length packets is described. The technique uses a plurality of police engines, grouped in pairs. A selection module selects a police engine pair to process a packet. Each police engine contains a conformance unit, credit unit and a debit unit, in which the credit update of one police engine influences the credit update of the other police engine in the pair. The technique also uses a combinatorial function to decide on a category of a processed packet and which police engines to update their debit units.

Abstract: A spirometer coupled to a manual resuscitator. An air tube in the spirometer has a converging section, a laminar flow section and a pressure recovery section. A microcontroller and a display of expiratory flow parameters is provided.

Abstract: An oscillating spray device comprising an oscillation chamber. A power nozzle for projecting a jet of liquid under pressure into the oscillation chamber in a given direction. A reversing member in the chamber has a reversing wall for reversing the direction of flow of the fluid jet in a direction 180° opposite the given direction. A system of vortices is formed thereby for alternately passing fluid to one side or the other of the reversing member. A pair of passages, one on each side of the reversing member, convey alternate pulses of fluid through the passageways in the given direction past the reversing member to an outlet to ambient, and an island barrier positioned in the outlet to ambient and forming two separate passageways to the outlet and a third passageway between the reversing member and the island barrier. The spray characteristics can be adjusted by changing the spacing between the reversing member and island barrier.

Abstract: The light bulb socket burnishing tool is a device used to remove surface corrosion from the interior of common light bulb sockets without their removal from a base, restoring to operation and extending the life of the socket.

Abstract: A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network.

Abstract: An optical network unit having an environmentally sealed printed circuit board arrangement within a first compartment and a signal in/out arrangement in a second compartment. The compartments are provided by two housings. Instead of replacing individual circuit boards in the case of breakdown or malfunction, replacement of the whole of the printed circuit board arrangement is necessary thereby eliminating human error and minimizing downtime. Two housings provide the two compartments. These housings are preferably mounted upon a housing mount and a carrier for the optical network unit is also preferably mounted upon the housing mount. This housing and carrier arrangement simplifies assembly and disassembly of parts of the unit for maintenance and replacement purposes.

Abstract: A therapeutic spa tub having a waterline and one or more fluidic nozzles for issuing therapeutic jets of water into the tub. The one or more water nozzles each comprises a housing having an inlet for receiving a flow of water under pressure, a fluidic oscillator having an oscillation chamber and at least one power nozzle coupled to the inlet and the oscillation chamber for projecting at least one jet of water into the oscillation chamber in one or more outlets from said oscillation chamber for issuing one or more pulsating jets of water into the spa tub below the waterline. An air passage in the outlet entrains ambient air in water passing through the outlet. The fluidic oscillator is a low frequency reversing chamber oscillator wherein the oscillation chamber has a reversing wall.

Abstract: A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.

Abstract: A system and method for increasing the data rate of a system bus without making modifications to existing (legacy) devices connected to the bus. A logical bus is overlaid onto one or more physical buses in a TDM manner. The overlaying is done by transmitting data into the one or more existing buses during a previously unused phase of the bus clock having no effect on existing devices connected to the buses. The additional devices are capable of latching data on either phase bus clock.