Patents Represented by Attorney Joe E. Barbee
  • Patent number: 6037789
    Abstract: Throughput and accuracy of testing of a semiconductor device is improved by forming the contacts to allow the leads of a packaged semiconductor device to pass through the contacts. Both AC and DC testing may be done because the contact length is substantially shortened.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: March 14, 2000
    Assignee: Motorola, Inc.
    Inventors: Milo W. Frisbie, Mavin C. Swapp
  • Patent number: 5898101
    Abstract: A method of operating chemical sensors (21) uses synchronously pulsed signals to reduce the power consumption of the chemical sensors (21). A first voltage source can be used to control and to heat multiple heating elements of the chemical sensors (21). The first voltage source can also be used to control other sensors which do not require elevated temperature operation. A second voltage source can be used to operate and bias the chemical sensors (21) heated by the multiple heating elements. Power consumption is reduced by turning or pulsing off the heating element (16) when it is not used.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: April 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Robert P. Lyle, Henry G. Hughes
  • Patent number: 5692873
    Abstract: An apparatus for and method of holding a semiconductor wafer (11) during a manufacturing process supports the semiconductor wafer (11) in a substantially planar form (15) with a two-platform wafer chuck (19). The two-platform wafer chuck (19) is compatible with handling warped and unwarped wafers, wafer transferring and handling techniques which maintain wafer flatness, and semiconductor manufacturing processes such as photolithography and auto-probing which require semiconductor wafers to be held in a flat configuration.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: December 2, 1997
    Assignee: Motorola, Inc.
    Inventors: Anthony R. Weeks, Todd R. Beasley, Craig D. Gordy
  • Patent number: 5650920
    Abstract: A transformer mount (11) supports a transformer (12) over a component (22) on a substrate (23) of a hybrid module (10). The transformer mount (11) conserves space in the hybrid module (10), improves high frequency performance by minimizing parasitic capacitances and inductances of the transformer mount (11), is compatible with subsequent high temperature and batch processing for faster assembly, permits the flow of defluxing materials beneath the transformer mount (11), is inexpensive, and provides appropriate access to fine tune the transformer (12) during assembly.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: July 22, 1997
    Assignee: Motorola, Inc.
    Inventor: Henry L. Pfizenmayer
  • Patent number: 5641712
    Abstract: A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: June 24, 1997
    Assignee: Motorola, Inc.
    Inventors: Gordon M. Grivna, Karl J. Johnson, Bruce A. Bernhardt
  • Patent number: 5635422
    Abstract: Dopants from a diffusion source (16) are diffused into a product wafer (14) to form a uniform doping concentration within the product wafer (14). The source (16) has a thermal conductivity that is approximately equal to a thermal conductivity of the wafer (14). The source (16) is positioned near the wafer (14) thereby forming a space (23) between the source (16) and the wafer (14). Gas flow (26) through the space (23) is limited to a predetermined value in order to prevent disturbing dopant diffusion. The source (16) is heated to a predetermined temperature, then the wafer (14) is heated. Subsequently, the wafer (14) and the source (16) are cooled at substantially equal rates.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: June 3, 1997
    Assignee: Motorola, Inc.
    Inventor: Bohumil Lojek
  • Patent number: 5578841
    Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: November 26, 1996
    Assignee: Motorola, Inc.
    Inventors: Barbara Vasquez, Irenee M. Pages, E. James Prendergast
  • Patent number: 5477467
    Abstract: A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: December 19, 1995
    Assignee: Motorola, Inc.
    Inventor: James M. Rugg
  • Patent number: 5469072
    Abstract: An integrated circuit test system provides a quick change flexible circuit membrane (214). The flexible circuit membrane is a quadrant based design which allows steep launch angles away from a rectangular die under test (112). The flexible circuit membrane is edge guided (308,309) for positioning and concentric alignment in a probe tooling fixture (212). The system may include a focusing force member (528) focusing force only at the test point locations in line with the die pad contact positions (512) which allows greater force to be concentrated on the contact area, and helps to alleviate the debris tracking or "dust mop" effect. Additionally, a relieved area (620) may be provided on the pressure applicator (616) to prevent membrane droop or the pillowing effects.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: November 21, 1995
    Assignee: Motorola, Inc.
    Inventors: William M. Williams, Anthony Angelo, Gregory L. Westbrook
  • Patent number: 5469263
    Abstract: A method for alignment in photolithographic processes includes providing a target (31) comprising features having a characteristic spatial period (P). An optical image of the target is captured, and components (33) of the image lacking the characteristic spatial period (P) are filtered out. The filtered image is integrated in the direction of the characteristic period (P) thereby creating an alignment signal (40). The alignment signal (40) is a symmetric signal which correlates to the symmetric target (31). A linear centroid (41) of the alignment signal is located, and corresponds to the precise linear center of the target (31). Consequently, the linear location of an object (10) upon which the target (31) is printed, can be accurately located. The process is performed in two perpendicular dimensions (x,y) so that the object (10) can be precisely located and positioned in two dimensions (x,y).
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: November 21, 1995
    Assignee: Motorola, Inc.
    Inventors: Whitson G. Waldo, III, Gong Chen, Franco Cerrina
  • Patent number: 5452368
    Abstract: A method of detecting defects (14, 16, 17, 44, 47, 49, and 51) in objects is presented. A first grey level image (18) of a first object (10) is formed and a second grey level image (19) of a second object (12) is formed. The first (18) and second (19) grey level images are converted to a first (21) and a second (22) edge feature image, respectively. The first edge feature image is dilated (26) and the second edge feature image is skeletonized (27). The dilated (26) and skeletonized images (27) are compared. An alternate method includes forming a grey level image (40) of an object. A principal axis of the grey level image is identified, and a shifted grey level image is formed by shifting the grey level image a distance along the principal axis. The grey level image (40) is then compared to the shifted grey level image.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: September 19, 1995
    Assignee: Motorola, Inc.
    Inventor: Christopher J. LeBeau
  • Patent number: 5442237
    Abstract: A semicondutor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18, 18') using a fluorinated polymer dielectric (14,14'). The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18, 18').
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: August 15, 1995
    Assignee: Motorola Inc.
    Inventors: Henry G. Hughes, Ping-Chang Lue, Frederick J. Robinson
  • Patent number: 5413952
    Abstract: A method for forming a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. By patterning the high temperature metal nitride layer (16) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal nitride layer (16) and a dielectric layer (17, 27) subsequently formed over the high temperature metal nitride layer (16) is significantly improved. The dielectric layer (17, 27) will adhere to the high temperature metal nitride layer (16) in high temperature environments. In addition, a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. The structure is suitable for power, logic, and high frequency integrated circuit devices.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: May 9, 1995
    Assignee: Motorola, Inc.
    Inventors: Irenee Pages, Francesco D'Aragona, James A. Sellers, Raymond C. Wells
  • Patent number: 5413965
    Abstract: A method for manufacturing a liquid-containing microelectronic device package. The method includes steps of providing (32) a base (16) including a microelectronic device (22) and a seal area disposed peripherally about the base (16), providing (34) a lid (12) and providing (34) a sealant (14) disposed between the base (16) and lid (12). The method also includes steps of immersing (36) the base (16), sealant (14) and lid (12) in a liquid (24) having a temperature above a sealant activation temperature and maintaining (38) the base (16), sealant (14) and lid (12) in the liquid (24) for a time sufficient to allow the liquid (24) to enter between the base (16) and lid (12) and to heat and thereby activate the sealant (14). The method further includes removing (40) the base (16), lid (12) and sealant (14) from the liquid (24) to provide a sealed, liquid-containing microelectronic device package (10).
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: May 9, 1995
    Assignee: Motorola, Inc.
    Inventors: Brian A. Webb, Robert M. Wentworth
  • Patent number: 5411629
    Abstract: A method for roughening a principal surface (12) of a halocarbon film (11). The halocarbon film (11) is treated with a colloidal suspension wherein the colloidal suspension includes light metal atoms. The light metal atoms combine with halogen atoms of the halocarbon film, thereby toughening the principal surface (12) and giving the principal surface (12) a burnt appearance.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: May 2, 1995
    Assignee: Motorola, Inc.
    Inventor: Timothy J. Warfield
  • Patent number: 5389576
    Abstract: A method substantially eliminating consumption of silicon from semiconductor devices is provided. The method includes controlling gases within the environment wherein the semiconductor device is positioned. The environment is formed to include an inert gas and oxygen. The oxygen content is formed to have a concentration between approximately 1.times.10.sup.1 and 1.times.10.sup.5 parts per million. Such an oxygen concentration substantially prevents converting silicon from the semiconductor device into silicon monoxide thereby substantially eliminating silicon consumption.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventor: Israel A. Lesk
  • Patent number: 5388323
    Abstract: A probe (10,30,40) for forming images of surfaces (11) facilitates simultaneous formation of both thermal and atomic force microsocopy images. The probe (10,30,40) includes a heat sensing assembly (15) that has a heat sensing element (19,38,42). An electrically isolating and thermally conductive tip (22,48) projects from the heat sensing assembly. The probe (10) also has a reflective element (24) that is positioned between a first end of the heat sensing assembly (15) and the electrically isolating and thermally conductive tip (22).
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventors: Theresa J. Hopson, Ronald N. Legge, Juan P. Carrejo
  • Patent number: 5389564
    Abstract: The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventors: Bruce A. Bernhardt, Jaeshin Cho, Gregory L. Hansell
  • Patent number: 5387548
    Abstract: The present invention includes forming an etched ohmic contact (10, 9) by applying a layer of an etch susceptible contact material (14) to a III-V semiconductor substrate (11). A portion of the contact layer (14A) is alloyed with the substrate (11) to form are etch resistant area (14A) of the contact layer. The contact layer (14) is selectively etched to remove etch susceptible portions of the contact layer while leaving the etch resistant area (14A) on the substrate (11). Another alloy operation is performed to form ohmic contact between the etch resistant area (14A) and the substrate (11). Consequently, an etch ohmic contact (10, 9) that is substantially devoid of gold is formed.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: February 7, 1995
    Assignee: Motorola, Inc.
    Inventor: Jaeshin Cho
  • Patent number: RE36890
    Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: October 3, 2000
    Assignee: Motorola, Inc.
    Inventors: Raymond C. Wells, Frank T. Secco d'Aragona