Abstract: A method for making a shallow junction in a gallium arsenide substrate including implanting doping ions into an upper surface of the substrate and incorporating sulfur into the upper surface of the substrate after the ion implantation. A capping layer is deposited on the upper surface and the substrate is heat annealed to activate the doping atoms.

Abstract: Testing of a semiconductor device (10, 30) is facilitated by forming the semiconductor device (10, 30) to have a first portion (17) that is electrically isolated from a second portion (19, 27). Testing is first performed on the first portion (17) of the semiconductor device (10, 30). After the testing is complete, the first portion (17) of the semiconductor device (10, 30) is electrically coupled to the second portion (19, 27) of the semiconductor device (10, 30) .

Abstract: An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.

Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21 ) , and the second porous die mount (22 ) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20) , the first porous die mount (21) , and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.

Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A IV--IV semiconductor device having a narrowed bandgap characteristic compared to silicon and method is provided. By incorporating carbon into silicon at a substitutional concentration of between 0.5% and 1.1%, a semiconductor device having a narrowed bandgap compared to silicon and good crystalline quality is achieved. The semiconductor device is suitable for semiconductor heterojunction devices that use narrowed bandgap regions.

Abstract: A lateral bipolar transistor (10) includes a retrograde doping profile (21) that is formed within a substrate (11) to form the transistor's (10) collector region (14). A base region (16) that includes an inactive base area and an active base area (17) is formed in the collector region (14). An emitter (18) is formed within the active base area (17) wherein current (22) flows through the emitter (18) through the active base area (17) and through the collector region (14). The base region, the emitter, and a collector contact region are all formed by driving dopants from an overlying polysilicon layer.

Abstract: A probe (10,30,40) for forming images of surfaces (11) facilitates simultaneous formation of both thermal and atomic force microsocopy images. The probe (10,30,40) includes a heat sensing assembly (15) that has a heat sensing element (19,38,42). An electrically isolating and thermally conductive tip (22,48) projects from the heat sensing assembly. The probe (10) also has a reflective element (24) that is positioned between a first end of the heat sensing assembly (15) and the electrically isolating and thermally conductive tip (22).

Abstract: A semiconductor sensor (10) is built into a cable connector to provide rapid and reliable attachment of the semiconductor sensor (10) into a monitoring or control system. The sensor (10) is mounted in a package (11) having cable connector leads (12, 13, 14) extending through the package (11). The semiconductor sensor (10) is electrically attached to the cable connector leads (12, 13, 14). A housing (20,30) surrounds the package (11) and provides a protective shroud for the cable connector leads (12, 13, 14).

Abstract: The topography of a surface is measured by utilizing a probe (10, 20) having a variable flexibility and a conductive tip (14, 16). Using the conductive tip (14, 16), a first tunneling current is measured at a first point (36). The tip (14, 16) is moved to a second point (37) and a deflection force is measured. The measurements from the different points (36, 37, 38, 39, 40, 41) are combined to provide composite images of the surface's topography and material composition.

Abstract: A micromachined capacitor structure having a first anchor (12) attached to the substrate (24), a tether (13) coupled to the anchor (12) and having a portion free to move in a lateral direction over the substrate (24) in response to acceleration. A tie-bar (14) is coupled to the movable portion of the tether (13), and at least one movable capacitor plate (16) is coupled to the tie bar (13). A first fixed capacitor plate (16) is attached to the substrate (24) laterally overlapping and vertically spaced from the at least one movable capacitor plate (16).

Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.

Abstract: A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).

Abstract: A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.

Abstract: A collector arrangement for a magnetotransistor (10, 25, 30) and a method for making the magnetotransistor (10, 25, 30). A portion of a semiconductor substrate (11) is doped to form a base region (13). The base region is doped to form an emitter region (16, 26, 36) and a collector region (17, 27, 37) such that the collector region (17, 27, 37) surrounds and is spaced apart from the emitter region (16, 26, 36). Collector contacts (C.sub.1 -C.sub.8 and C.sub.5 '-C.sub.8 ', C.sub.13 -C.sub.16) are symmetrically formed in the collector region (17, 27, 37). In a three-dimensional magnetotransistor (10, 25) the collector contacts include split-collector contacts (C.sub.5 -C.sub.8 and C.sub.5 '-C.sub.8 ').

Abstract: The present invention provides an amplifier arrangement to which feed forward correction is applied by a comparison loop including comparison means for comparing amplifier input with amplifier output to provide an error signal, a cancellation loop including secondary amplifier means for amplifying the error signal and combining means for combining said amplified signal with said amplifier output, a pilot generator coupled to said amplifier input to introduce a pilot tone therein, detector means for detecting a level of pilot tone in said amplifier output and correction means for correcting said cancellation loop performance as a function of said detection wherein said pilot generator is further coupled to a multiplier receiving said amplifier output, said multiplier producing an output signal arranged to control a loop parameter to effect said correction.

Abstract: A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.

Abstract: Briefly stated, the present invention provides a vertical current flow semiconductor device (17). The vertical current flow semiconductor device (17) includes a semiconductor substrate (12) having an intermediate conductor layer (16) on a surface of the substrate (12). An active layer (11) that is used for forming active elements (20, 21, 22, 23) of the vertical current flow semiconductor device (17) is on the intermediate conductor layer (16). The intermediate conductor layer (16) forms an ohmic contact with the active layer (11).

Abstract: A memory structure and related method for collecting and maintaining data descriptive of a multiplicity of interrelated process flows is disclosed. A complex memory structure includes job entities, operation entities, and process entities. Operation entities are subordinate to job entities, and process entities are subordinate to operation entities. These entities are represented by tables which are linked together to indicate their position in the hierarchy and their sequencing within a process flow. The process entities describe specific activities accomplished by an organization in achieving organizational goals. Typically, resources are either consumed or released, or both, during a process. Bill-of-resource tables are subordinate to process entities and populated with data which identify resources consumed by corresponding processes in the process flow.