Abstract: A method for joining a number of first and second wafers (11,12) having one polished surface in preparation for direct wafer bonding is provided. The method involves placing a number of first (11) and the same number of second (12) wafers into slots (16) of a retainer (14) so that each of the polished surfaces of the number of first wafers (11) is forced to contact one of the polished surfaces of the number of second wafers (12).

Abstract: A method of decoupling a step for modulating a defect density from a step for modulating a junction depth. A semiconductor substrate (30) having a portion doped with a dopant (34) is heated to a pre-oxidation anneal temperature in a pre-oxidation anneal step (23). After the pre-oxidation anneal step (23), the semiconductor substrate (30) undergoes an oxidation step (25) which serves as a step for modulating the defect density. Subsequent to the oxidation step (25), the semiconductor substrate (30) undergoes a drive-in step (27) which serves as a step for modulating the junction depth. Then, the temperature of the semiconductor substrate (30) is lowered to allow further processing of the semiconductor substrate (30).

Abstract: A portable interprocess communication facility by which different processes running simultaneously on a network of computer systems can efficiently communicate variable sized data blocks between each other. This involves the elements and techniques necessary to achieve high speed communication, without requiring the processes to be located on the same physical system or to be completely dependant upon the particular design or revision of the operating system in which they run. In addition, the invention simplifies the task of porting a modular software system between different hardware devices and operating systems by allowing communicating processes to be only loosely connected to the operating system.

Abstract: The present invention includes a semiconductor package (20) that has a leadframe (10). An insulator (13) is mounted on a surface of a flag (11) of the leadframe (10) to insulate a portion of the leadframe (10) from the external environment. A semiconductor die (16) is also mounted on the flag (11), spaced away from the insulator (13). A portion of the leadframe (10), the semiconductor die (16), and a portion of the insulator (13) are encapsulated by a body (21) of the package (20). The body (21) also has an alignment hole (23) that extends from a surface of the body to the insulator (13), and exposes a portion of a surface of the insulator (13). In addition, the body (21) overlaps the insulator (13) and forms a seal to the insulator (13) protecting the leadframe (10) from the external environment.

Abstract: A low inductance lead frame (10) is formed to have a die attach area (11). A plurality of intermediate connection bars (12,13,14,15) are positioned to be parallel to sides of the die attach area (11), and to be in a plane that is displaced perpendicularly from the die attach area (11). Each end of each intermediate connection bar is separated from an end of each other intermediate connection bar. Supports (17) extend from the die attach area (11) to the intermediate connection bars (12,13,14,15) to provide support for the intermediate connection bars 12,13,14,15). A plurality of leads (19,33,34) are positional in a plane and have a proximal end near the intermediate connection bars (12,13,14,15).

Abstract: A substantially planar insulating sheet of high temperature printed circuit board material (11) is used to form a leadframe strip (18, 19, 21) for a semiconductor package (20). The leadframe strip (18, 19, 21) includes a die attach opening (12) through the insulating sheet (11). A plurality of metallized areas (13, 22, 23) on the insulating sheet (11) form bonding pads (13) and package leads (22). Conductive holes (14) electrically connect the bonding pads (13) and the package leads (22).

Abstract: An ion implantation apparatus including a resolving aperture-shutter assembly (31) placed in the ion beam path (18). The resolving aperture-shutter assembly includes a movable shutter (34) and a shutter housing surrounding the movable shutter (34). Selected ions in an ion beam path (18) pass through a hole (44) in movable shutter (34) when the movable shutter (34) is in a first position, and are blocked by the solid surfaces when the movable shutter (34) is in a second position. The enclosure (32, 33, 39) completely surrounds the movable shutter (34). The enclosure (32, 33, 39) includes a first aperture (42) aligned with the ion beam path (18) for allowing the selected ions to enter the enclosure and a second aperture (41) aligned with the ion beam path (18) for allowing the selected ions to exit the enclosure after passing through the hole (44) in the movable shutter.

Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

Abstract: A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.

Abstract: A semiconductor wafer (40) is placed in a first pressure chamber (37) of a bonding apparatus (10 or 60). A major surface (46) of a submount (44) is placed on a submount support (30 or 62). The major surface (46) of the submount (44) seals the first pressure chamber (37). A pressure differential is generated between the first pressure chamber (37) and a second pressure chamber (47) The pressure differential bows a central portion of the submount (44) toward the semiconductor wafer (40). The central portion of the submount (44) contacts an adhesive coating over a central portion of the semiconductor wafer (40). The submount support (30 or 62) is displaced to decrease a curvature on the submount (44). The pressure differential is increased to an end-point to facilitate bond formation between the semiconductor wafer (40) and the submount (44).

Abstract: A semiconductor structure that provides intrinsic doping from native defects is provided. A quantum well including a narrow bandgap material (11, 14) having a low concentration of native defects is sandwiched between two wide bandgap spacer layers (12, 20, 17, 15). The spacer layers (12, 20, 17, 15) have a low concentration of native defects. At least one doping region (13, 16) having a high concentration of native defects positioned adjacent to one of the undoped spacer layers (12, 17).

Abstract: A high transconductance HFET (21) utilizes nonalloy semiconductor materials (26) to form a strained channel layer (26) that has a deep quantum well (38). The materials utilized for layers adjacent to the channel layer (26) apply strain to the channel layer (26) and create an excess of high mobility carriers in the channel layer (26). The materials also form a deep quantum well (38) that confines the high mobility carriers to the channel (26). The high mobility carriers and the high confinement provide an HFET (21) that has high transconductance, high frequency response, and sharp pinch-off characteristics.

Abstract: A differential ECL signal is converted to a first current and a second current that are proportional to the ECL signal. An upper output transistor (16) and a lower output transistor (57) are selectively enabled and disabled by the first current. The second current is used to enable discharging of a storage capacitance of the lower output transistor (57) thereby substantially disabling the lower output transistor (57) before the upper output transistor (16) is enabled. In addition, a capacitor is used to momentarily discharge the storage capacitance as the upper output transistor (16) is enabled. The capacitor is discharged when the upper output transistor (16) is disabled.

Abstract: A plurality of piezoelectric resonators (10,32,37,57,62,66,79,88,93) are utilized to form a bandpass filter (31,56,78). The resonators (10,32,37,57,62,66,79,88,93) are connected in parallel to form a plurality of parallel paths between an input (43,73,81) and an output (47,74,82) of the filter (31,56,78). A predetermined number of the piezoelectric resonators (10,32,37,57,62,66,79,88,93) provide a phase shift of approximately 180 degrees. Each parallel path has a passband and center frequency that is displaced from the passband and center frequency of other paths. Consequently, the passband of each parallel path algebraically sums and creates a filter passband that is wider than the passband of each of the filter's individual parallel paths.

Abstract: A method for forming a plurality of surface conduction paths (33) in a conductive region (16) of a first conductivity type. A plurality of areas (17) of a second conductivity type are formed in the conductive region (16). The plurality of areas (17) deplete the conductive region (16) when a reverse bias voltage is placed across the conductive region (16) and the plurality of areas (17). Area of the conductive region (16) adjacent to each of the plurality of areas (17) form the plurality of surface conduction paths (33) for conducting current through the conductive region (16).

Abstract: A sealed container (10) having a plurality of compartments. A first compartment (11) has a window (15) with a transparent panel. A humidity indicator device (16) is placed within the first compartment (11). A second compartment (12) is coupled to the first compartment (11) by a plurality of environmental exchange channels (17). At least one article (27), such as plastic encapsulated electronic components, is stored in the second compartment (12). A third compartment (13) is coupled to the second compartment (12) by a plurality of moisture transport channels (20). A desiccant (31) is placed in the third compartment (13). An internal environment of the sealed container (10) is monitored by viewing the humidity indicator device (16) through the window (15).

Abstract: A memory system, having security against unauthorized accessing of the contents of the memory system, comprises a first alterable memory (6), a second non-alterable memory (14, 16) and a data bus (5) for allowing external access to data stored in the memory system during a test mode of operation. The first alterable memory (6) comprises an options register (10) having a security bit (SEC) which, when programmed to an active state, prevents external access to the data stored in the first alterable memory during the test mode. The first alterable memory (6) further comprises a first data memory (8) having at least one security byte (VALSEC) which, when programmed to a predetermined state, prevents external access to the data stored in both the first alterable memory (6) and the second non-alterable memory (14, 16) during the test mode.

Abstract: A microprocessor having a monolithically integrated environmental sensor is provided. The microprocessor is shielded from an environmental signal by isolation which is specific to the type of sensor used, thereby allowing the sensor to be exposed to the environmental signal. Optionally, high current drive circuitry is integrated with the microprocessor-sensor circuit to provide a monolithic device which allows control of power loads based in part on output from an environmental sensing device.

Abstract: A system and process for allowing virtual allocations of resources to lots to closely mimic actual allocations of resources to lots is disclosed. Virtual allocations represent planned or scheduled allocations of an organization's resources to produce various products. Actual allocations represent the actual course of events which occur while the product is being manufactured. A manufacturing interpreter interactively functions with an expert in a manufacturing environment to produce a comprehensive and accurate definition of resources utilized in a manufacturing environment. The manufacturing interpreter further allows the expert to define a comprehensive and accurate process flow description for various products. The process flow description specifies the resources, resource attribute capabilities, and order for applying resources to a single lot to produce a completed product.

Abstract: A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).