Patents Represented by Attorney John A. Fisher

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  • Fully differential switched capacitor amplifier having autozeroed common-mode feedback
    Patent number: 4697152
    Abstract: A fully differential amplifier which is compensated for both input offset voltage error and output common-mode variation is provided. The differential amplifier provides two very accurate output reference voltages which vary in proportion to the difference between first and second input voltages. In one form, the differential amplifier functions as an integrator. A differential amplifier is provided which uses first and second input pairs of differential transistors for normal differential operation and for common-mode output voltage regulation, respectively. Both input pairs of transistors must be compensated for offset voltage associated therewith. A compensation portion external to the differential amplifier is used to compensate for an offset voltage associated with circuitry within the differential amplifier for regulating the common-mode output voltage.
    Type: Grant
    Filed: April 11, 1986
    Date of Patent: September 29, 1987
    Assignee: Motorola, Inc.
    Inventor: Alan L. Westwick
  • Trench formation process
    Patent number: 4693781
    Abstract: A process is disclosed for fabricating a semiconductor device which includes a trench formed at the surface of the device substrate. The surface of the device substrate is oxidized and the oxide is patterned to form an opening which exposes a portion of the underlying surface. Ions are implanted through the opening and into the surface to form a damaged surface region which is coincident with the opening and extends under the edge of the oxide. A trench is etched by reactive ion etching using the opening in the oxide as an etch mask. The substrate, including the walls of the trench and the ion implant damaged surface portion under the edge of the oxide, is thermally oxidized. The oxidation rate is enhanced by the damage and causes a thicker oxide to grow in the damaged region which forms a collar around the intersection of the trench with the surface.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: September 15, 1987
    Assignee: Motorola, Inc.
    Inventors: Howard K. H. Leung, Bich-Yen Nguyen, John R. Alvis, John Schmiesing
  • Redundant column substitution architecture with improved column access time
    Patent number: 4691300
    Abstract: An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.
    Type: Grant
    Filed: December 20, 1985
    Date of Patent: September 1, 1987
    Assignee: Motorola, Inc.
    Inventors: Perry H. Pelley, III, Alan Lewandowski
  • One hundred percent duty cycle sample-and-hold circuit
    Patent number: 4691125
    Abstract: A switched capacitor sample-and-hold circuit which compensates offset voltage error and switch feedthru error while having a one hundred percent duty cycle is provided. Two amplifiers are utilized. A first operational amplifier is disconnected from a second operational amplifier while being autozeroed. An input voltage is sampled onto an input capacitor. The input capacitor is disconnected from the input voltage and then coupled to the second operational amplifier which is in a unity gain configuration. After the sampled input voltage is charged onto an output load, the first operational amplifier is disconnected from the second operational amplifier and the sampling process is repeated. The second operational amplifier is also offset voltage compensated by the first operational amplifier.
    Type: Grant
    Filed: October 3, 1986
    Date of Patent: September 1, 1987
    Assignee: Motorola, Inc.
    Inventor: Mathew A. Rybicki
  • Memory with improved write mode to read mode transition
    Patent number: 4689771
    Abstract: A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.
    Type: Grant
    Filed: March 3, 1986
    Date of Patent: August 25, 1987
    Assignee: Motorola, Inc.
    Inventors: Karl L. Wang, Mark D. Bader
  • High voltage decoder
    Patent number: 4689504
    Abstract: A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.
    Type: Grant
    Filed: December 20, 1985
    Date of Patent: August 25, 1987
    Assignee: Motorola, Inc.
    Inventors: Kuppuswamy Raghunathan, Jeffrey R. Jorvig, Stephen L. Smith
  • Method and apparatus for implementing a cost efficient voice/data communication system with a conventional PBX switch
    Patent number: 4689788
    Abstract: A method of providing simultaneous voice and data communication for multiple ports in a digital line card of a PBX is provided. In one form, 64 K baud non-blocking voice communication for seven coupled ports and simultaneous 9.6 K baud user data communication for each port may be implemented in a single conventional line card. Voice and data bits are transmitted in frames comprising thirty-two time slots. Data bits from the various user ports are multiplexed into a single eight bit time slot. Voice bits for each port are transmitted in eight bit time slots. In one form, each time frame comprises four time slots for data and twenty-eight time slots for voice.
    Type: Grant
    Filed: November 4, 1985
    Date of Patent: August 25, 1987
    Assignee: Motorola, Inc.
    Inventors: Henry Wurzburg, Stephen H. Kelley, Noel M. McCroskey
  • Multifunction analog-to-digital successive approximation register
    Patent number: 4688018
    Abstract: A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.
    Type: Grant
    Filed: September 16, 1985
    Date of Patent: August 18, 1987
    Assignee: Motorola, Inc.
    Inventor: Herchel A. Vaughn
  • Method and apparatus for access to a PLA
    Patent number: 4687959
    Abstract: Improved access to programmable logic arrays is provided by continuously asserting and negating a latch inputs control signal, continuously asserting and negating a control signal which discharges a first logic section of the array to provide frequent, current inputs to a second logic section of the PLA and discharging the second section of the PLA only upon receipt of an access request. In the case of asynchronous access, it is also necessary to generate a synchronized data strobe from the unsynchronized one and to generate an acknowledge signal to indicate the presence of valid output data. The disclosed method and apparatus provide access which has a short access time and which also provides outputs which reflect relatively current states of the inputs thereto.
    Type: Grant
    Filed: March 27, 1986
    Date of Patent: August 18, 1987
    Assignee: Motorola, Inc.
    Inventors: John K. Eitrheim, Ashok H. Someshwar
  • Integrated circuit trench cell
    Patent number: 4686552
    Abstract: A two-device trench cell having a transistor surrounded by a capacitor. This combined capacitor and transistor cell can be used as a memory cell. The capacitor is first fabricated into the walls of a trench leaving a narrowed trench into which a vertical metal-oxide-semiconductor field-effect-transistor (MOSFET) may be fabricated. One of the plates of the capacitor doubles as a source/drain layer of the transistor.
    Type: Grant
    Filed: May 20, 1986
    Date of Patent: August 11, 1987
    Assignee: Motorola, Inc.
    Inventors: Ker-Wen Teng, Bich-Yen Nguyen, Louis C. Parrillo
  • Floating point condition code generation
    Patent number: 4683546
    Abstract: A method and apparatus for generating floating point condition codes by using the data type of a result operand, rather than a magnitude relationship between two operands. The condition codes may then be combined to generate relations useful for identifying conditions for conditional branches or traps.
    Type: Grant
    Filed: October 14, 1986
    Date of Patent: July 28, 1987
    Assignee: Motorola, Inc.
    Inventor: Joel F. Boney
  • Method and apparatus for interfacing buses of different sizes
    Patent number: 4683534
    Abstract: In a data processing system having a first bus sized to accomodate 2.sup.x units of data and a second bus sized to accomodate 2.sup.y units of data, where x and y are positive integers and y is less than or equal to x, a method and apparatus for determining y from the x least significant bits of a control address, concatenated with a decode control bit, and then decoding the (x-y) most significant bits of the x control address bits to determine which of x data unit transceivers coupled between the first and second buses should be enabled.
    Type: Grant
    Filed: June 17, 1985
    Date of Patent: July 28, 1987
    Assignee: Motorola, Inc.
    Inventors: Donald L. Tietjen, Michael W. Cruess
  • Logarithmic arithmetic logic unit
    Patent number: 4682302
    Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.
    Type: Grant
    Filed: December 14, 1984
    Date of Patent: July 21, 1987
    Assignee: Motorola, Inc.
    Inventor: Tim A. Williams
  • Accelerated test apparatus and support logic for a content addressable memory
    Patent number: 4680760
    Abstract: Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Jesse R. Wilson, Terry V. Hulett
  • Integrated circuit packaging
    Patent number: 4680471
    Abstract: An integrated circuit comprising: a semiconductor die having an integrated circuit formed therein; a package for supporting the die and for providing electrical contact thereto, the radiation properties of the package having been characterized as follows: fabricating a detector using a semiconductor fabrication technique, the detector having substantially the same dimensions as an integrated circuit to be packaged in the packaging materia; packaging the detector using integrated circuit packaging techniques; and measuring the radiation environment of the detector.
    Type: Grant
    Filed: March 20, 1985
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Steven L. Morris, Gary C. Lewis
  • Dry etching of multi-layer structures
    Patent number: 4680086
    Abstract: A method for etching multi-layer structures particularly suited for patterning refractory metal silicide/polysilicon sandwiches. A first dry etch process is carried out in a first dry etch chamber and is selected to rapidly and anisotropically etch the uppermost layer, typically a refractory metal silicide. A second dry etch process is carried out in a second etch chamber and is selected to rapidly and anisotropically etch the underlying layer, typically polysilicon, while having a high selectivity to any material underlying the underlying layer. The first process is preferably a fluorine-chemistry process with low frequency RF energy and the substrate resting on the grounded electrode. The second process is preferrably a chlorine-chemistry process with high frequency RF energy and the substrate resting on the powered electrode.
    Type: Grant
    Filed: March 20, 1986
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Patrick K. Thomas, Dennis C. Hartman, Jasper W. Dockrey
  • Load double test instruction
    Patent number: 4679194
    Abstract: In a data processor having an instruction which requires the loading of the contents of two (2) successive locations in the address space during respective bus cycles, test circuitry is provided to selectively force the processor to twice load the contents of the same location upon execution of the instruction. Using this special load double test instruction, the processor is able to detect more precisely when the contents of the memory location changes in value as a result of the activity of other circuitry.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: July 7, 1987
    Assignee: Motorola, Inc.
    Inventors: Tulley M. Peters, William C. Bruce, Jr.
  • MOS transistor
    Patent number: 4675713
    Abstract: An improved MOS transistor and method for making that transistor are provided. The improved transistor is characterized by decreased size, improved switching speed, and improved reliability in inductive load use. The improved structure is achieved through the use of a low minority carrier injecting source region formed, for example, by providing a low barrier height metal silicide. The metal silicide source provides a source of majority carriers but little minority carrier injection and hence little parasitic bipolar transistor action.
    Type: Grant
    Filed: August 12, 1985
    Date of Patent: June 23, 1987
    Assignee: Motorola, Inc.
    Inventors: Lewis E. Terry, Emily M. Thompson
  • Continuous ionizer for semiconductor manufacturing processes
    Patent number: 4673443
    Abstract: A continuous ionizer adapted to introduce selected ions into a continually flowing stream of liquid. To ensure that a maximum concentration of ions is incorporated, the continuous ionizer is configured so that turbulent and intimate mixing of the ionizing gas and liquid to be ionized occurs. The flow of ionizing gas is regulated by a liquid level sensor to prevent a gas/liquid mixture from proceeding downstream from the ionizer. The apparatus and method of this invention are particularly suited to situations where deionized water is used in a process which causes undesired static electricity discharges, and clean, ion-possessing water is preferred, such as semiconductor processing.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: June 16, 1987
    Assignee: Motorola, Inc.
    Inventor: Allan M. Fetty
  • Built in self test input generator for programmable logic arrays
    Patent number: 4672610
    Abstract: A built in self test input generator (BISTIG) for programmable logic arrays (PLAs) providing exhaustive fault coverage, but requiring additional space of only 8 to 15% of the PLA area. The BISTIG contains a test vector generator and a product term control, each of which has a sequence generator and associated decoder. The sequence generators generate log.sub.2 (N) and log.sub.2 (M) test vectors for the test vector generator and the product term control respectively, where N is the number of inputs to the PLA and M is the number of product terms connecting the first level of the PLA with the second level of the PLA.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: June 9, 1987
    Assignee: Motorola, Inc.
    Inventor: John E. Salick