Abstract: A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.

Abstract: A non-volatile memory has memory cells which have a first or a second conductivity. A reference current is established through an unprogrammed reference cell which has the first conductivity. A logic state current is established through a selected memory cell. The magnitude of the logic state current is related to the conductivity of the selected memory cell. A current comparator is used to compare the reference current to the logic state current. If the logic state current is related to the first conductivity state, an output signal is provided at a first logic state. If the logic state current is related to the second conductivity state, the output signal is provided at a second logic state.

Abstract: A high gate output stage for use with an amplifier which has high power supply rejection and which is stable at all frequencies is provided. An output current source and current sink are connected in series with a Miller capacitor coupled between an input terminal and output terminal of the output stage. Error signals coupled from a power supply source are allowed to sum at the output terminal with a compensating signal. Compensation circuitry is coupled to the input terminal for charge coupling a substantially equal but opposite amount of compensation charge related to the error signal from the power supply, thereby substantially cancelling power supply error signal coupling. Therefore, excellent power supply rejection and frequency stability are provided in a high gain output stage.

Abstract: A memory is comprised of memory cells located at intersections of word lines and bit line pairs. The memory has a read mode in which data is read from a bit line pair selected by a column address. The data to be read is provided to bit line pairs by the memory cells which are coupled to a word line which has been selected to be enabled by a row address. In the write mode, data is written to a memory cell which is coupled to an enabled word line and which is coupled to a bit line pair into which data has been selected to be written. The pairs of bit lines are equalized in voltage in response to not only an address transition but also in response to a transition from the write mode to the read mode.

Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

Abstract: Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a data line while the sense amplifier is amplifying the signal provided by the memory cell. The effect of coupling the bit line to the data line is to hinder the refresh of the selected memory cell because the bit line does not reach full power supply voltage due to the loading by the data line. Full refresh is obtained by keeping the word line enabled for a predetermined time following the bit line being decoupled from the data line so the sense amplifier can bring the bit line to full power supply potential.

Abstract: A data processor control unit which provides instructions for execution by a data processor and minimizes instruction cycles lost as overhead. A pipelined instruction stream is used in which instruction addresses are selectively coupled from a program counter and a prefetch counter to a program memory which provides actual instructions. The instructions are stored in a prefetched register, decoded and then loaded into an instruction register coupled to the data processor. When an interrupt service request is made by a device peripheral to the processor, the prefetch instruction address flow is immediately redirected and a predetermined number of interrupt instruction words are prefetched by an interrupt address generator before completion of execution of normal program instructions has occurred. Therefore, interrupt instructions are fetched and jammed into a pipelined instruction stream regardless of instruction cycle boundaries.

Abstract: A process is disclosed for fabricating a free-standing thin or thick film structure. One embodiment of the process includes the steps of providing a substrate of a first refractory material, forming a layer of carbon on the substrate, and depositing a film of a second refractory material on top of the layer of carbon. This sandwich structure is heated in an oxidizing ambient to cause the oxidation of the carbon layer leaving the second refractory material as a free-standing film.

Abstract: A differential amplifier is provided which has a low systematic offset voltage and a small variation in quiescent current with respect to variations in processing and temperature while providing low input referred noise and good output drive capability. Each transistor of a differential input pair of transistors is coupled to a plurality of series-connected transistors which are fabricated with substantially equal control electrode dimensions to form composite load tranistors. An output stage having conventional source and sink transistors is coupled to the differential pair of transistors. The sink transistor is implemented as a composite transistor by a plurality of parallel-connected transistors, each also having substantially the same control electrode dimension. Since all the ratioed transistors have equal control electrode dimensions, variations over processing and temperature are minimized.

Abstract: A memory has input buffer which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer includes an input inverter with hysteresis as well as a cross coupled latched for avoiding problems with a slow moving input signal. The cross coupled latch is a NAND gate latch to provide for a quick logic low to logic high transition which is favorable for quick transition detection. A second inverter provides a feedback signal to a feedback transistor which provides hysteresis for the first inverter. A load is placed in series with the feedback transistor for use in obtaining the desired hysteresis. The feedback transistor can thus have a minimum gate area to minimize the capacitance added by the feedback transistor to the output of the second inverter while the load can be varied as desired for optimizing the hysteresis.

Abstract: A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.

Abstract: An MOS capacitive structure comprising a substrate of a first conductivity type, a first region of the first conductivity type but having a different impurity concentration for contacting the substrate, a second region of opposite conductivity type for contacting the substrate, and a dielectric over a region of the substrate adjacent the first and second regions and having a conductive layer thereon forming one plate of the capacitor while the substrate opposite the conductive layer forms the other plate. The first and second regions are contacted and coupled together in order to provide good electrical contact to the substrate region opposite the conductive layer regardless of whether the substrate under the conductive layer is depleted or inverted.

Abstract: A one step metallization is disclosed for applying a layer of gold or gold alloy to the back of a silicon substrate to facilitate bonding that substrate to a metallized package member. The gold is applied to the substrate, for example by evaporation, while the substrate is maintained at a temperature between about 200.degree. C. and about 360.degree. C. Following the deposition the substrate is quickly cooled to room temperature. The thickness of the gold layer and the deposition temperature are adjusted to insure that the silicon diffusion profile is contained within the gold film during deposition. This insures good adhesion of the gold to the silicon substrate and provides a pure gold surface layer necessary for optimum bonding of the semiconductor substrate to a metallized package portion.

Abstract: A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.

Abstract: A process and apparatus for LPCVD of thin metallic films is disclosed. The apparatus includes a U-shaped injection tube through which high molecular weight reactants are injected into a reaction chamber. The input and output ends of the U-shaped tube are coupled to a removeable feedthrough plate which, in turn, is coupled to the end cap which seals one end of the reaction chamber. A deposition surface is placed in the chamber through a second end cap at the opposite end of the chamber. The output end of the U-shaped injection tube is coupled to a vacuum pump and the high molecular weight reactant is drawn through the injection tube and dispersed in the reaction chamber through a plurality of holes in the input side of the injection tube.

Abstract: A voltage regulator circuit which provides a regulated output voltage by regulating output current at an output terminal is provided. The voltage regulator circuit operates in response to a clocked control signal. The regulated output voltage and a delayed signal of the regulated output voltage are both used to bias a selected one of series-connected transistors which sink current from the output terminal in response to the value of the output voltage and the frequency of the clocked control signal. A second control signal is provided for enabling or disabling the voltage regulator circuit.

Abstract: An integrated circuit test site assembly for testing pin grid array (PGA) packaged integrated circuits having removable contact pins. The removable contact pins, which are preferably spring-loaded pogo pins, enable the test site assembly to be repaired quickly and easily with a minimum of down time. In addition, the test site need only be loaded with the number of pins required to make contact with the PGA lead pattern.

Abstract: A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders

Abstract: An integrated circuit microcomputer with EEPROM has a limited number of modes for operation. In at least first and second modes, the inner workings of the microcomputer, including the contents of the EEPROM, can be read externally from the microcomputer. An EEPROM security bit, when set, prevents the first mode from being entered and causes the EEPROM to be erased when the second mode is entered. The EEPROM is also erased if the security bit is erased.

Abstract: An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.