Abstract: A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce an output signal which is indicative of the correlation between the received PN code and the locally generated PN code as compared against a programmable threshold. The programmable detector logic is capable of detecting acquisition correlation and tracking correlation and can optionally inform an external microprocessor of the correlation level so as to implement a wide variety of acquisition, tracking and reacquisition algorithms as well as optional AM demodulation.

Abstract: A system for determining attitude of airborne vehicles or surface vehicles is provided with three fixed position antennas separated from each other by a predetermined calibrated distance. Each antenna is connected to a GPS receiver and the receiver outputs are coupled to a phase comparator which establishes the phase difference between the RF carrier signal of the three possible pairs of receivers. The outputs of the phase comparator are coupled to a preprogrammed dedicated processor that calculates a coordinate frame which fixes the attitude of the plurality of antennas in space. The processor then makes a comparison with a precalibrated reference attitude stored in an associated memory so that a true attitude value of roll, pitch and yaw may be calculated and employed to reposition the gyro of the moving vehicle.

Abstract: A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and down counter having a number of most significant bit stages. The adder stages of the input accumulator have their carry and borrow outputs coupled to the up and down counter for generating additional most significant bits.

Abstract: A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.

Abstract: A text orientation system for dot matrix printers includes a character adjust logic for orienting an image to be printed relative to a physical page. A first register in the character adjust logic receives a word of memory for either placement or character address. Each word has base bits and orientation bits. When the word is for address, the first register separates the base bits from the orientation bits and forwards the base bits to an adder and the orientation bits to an orientation adjust logic. Other bits of orientation adjust from a character processor are loaded into a second register and then to the orientation adjust logic for combining with orientation bits. A resulting adjusted signal goes to a Mux for selecting a displacement to produce a displacement signal. The displacement signal is then added to the previously separated base bits and forwarded as an adjusted character address to a character generator address.

Abstract: A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts and includes staging buffers coupled to the main bus and data buffers coupled to the data bus. A J-Bus is coupled between the staging buffers and the data buffers and is controlled by J-Bus transfer controller. A D-Bus transfer controller controls information transferred to an from the data bus and the data buffers. An M-Bus transfer controller controls information transferred to and from the staging buffers and the M-Bus. A controllable time slot generator in addition to generating the time slots for transferring information between the data buffers on the J-Bus also provides means for resolving conflicts between the J-Bus and the D-Bus and the M-Bus.

Abstract: A light concentrating cluster mount for super bright light emitting diodes is provided. The cluster mount is provided with a plurality of LED receivers therein. Said cluster mount has a central axis and each of the LED receivers has a focus axis displaced from the central axis and is focused to cross the central axis at a predetermined distance from the cluster mount so that the side light and the frontal light emitted from each of the light emitting diodes is refocused on to area to be illuminated at a predetermined distance from the cluster mount.

Abstract: Apparatus for shifting the output of a bit matrix character generator ninety degrees to provide ninety degrees shifted characters and comprises a barrel shifter for barrel shifting bit slices of the bit matrix characters coupled to a linear array shifter for linear array shifting the information that was first barrel shifted. A feedback loop which includes a rotate RAM memory having its output connected to the input of the barrel shifter means to twice barrel shift the information which was previously barrel shifted and then linear array shifted to provide a bit matrix character output which is rotated ninety degrees from the original bit matrix character provided at the output of the character generator.

Abstract: A zero clearance fireplace of the type adapted to be installed against an outside wall of an interior space or room to be heated is provided with six walls which comprise four substantially vertical walls, a top wall and a bottom wall at least two of said vertical walls having airtight glass side walls connected to the frame structure of the fireplace. The bottom wall, the vertical side wall and the top wall are provided with plenum structures which are inner connected to form a heat exchanger. The rear wall is provided with a vertical inner plenum in which outside fresh air is introduced and conducted into a bottom inner plenum below the combustion chamber of the fireplace to provide fresh outside air to the gas burner system in the combustion chamber.

Abstract: The present invention provides a novel programmable data communications controller employed to accept data from a host computing system and for transmitting the data to a terminal designated by the host computer system. The data computer communications controller is further provided with protocols, parameters and poll tables stored in a dedicated memory of the data communications controller which enables the controller to receive data and address information from a main memory of a host computer and to reformat and pre-package the information in a protocol format block acceptable by a terminal coupled to the data communications controller. Different protocols, parameters and polls are provided in the data communications controller in the form of preprogrammed information which enables different terminals employing different protocols and protocol formats to be coupled directly to a data link interface bus without hardware modifications.

Abstract: In a communications data link network of the type having a plurality of ground stations and a single moving airborne station, there is provided a doppler frequency compensation circuit in each of the ground stations. The downlink carrier frequency is fixed and continuously broadcast to the receiving ground station which continuously receive the doppler shifted carrier signal. The ground stations are provided with coherent demodulators which provide a coherent I.F. recovered carrier signal that is applied to a scaling phase-locked loop to provide a deviation frequency signal that is applied to an inverting phase-locked loop which provides a pre-compensated uplink R.F. carrier signal. The uplink R.F. carrier signal has a compensated uplink doppler frequency component which equals the inverted and scaled doppler frequency of the received downlink carrier.

Abstract: A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.

Abstract: A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.

Abstract: A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.

Abstract: A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

Abstract: An integrated priority network is provided for a bus architecture computing system of the type employing a M-Bus connected to a plurality of functional elements. Each functional element has its own integrated priority resolution network (IPRN) coupled to said M-Bus for activating its own unique individual priority request and for receiving all individual priority requests from all other functional elements. Each integrated priority resolution network unit is provided with a rotational priority circuit and a preemptive priority circuit connected in parallel and operable independently to produce a request granted signal. Logic circuits in each rotational priority circuit determine when an IPRN unit will be granted its priority request for access to said M-Bus and will block future requests from being activated to its IPRN unit until the other IPRN unit values in the rotational priority register of the rotational priority circuit have been granted access to said M-Bus.

Abstract: In a demodulator circuit for receiving a direct sequence spread spectrum signal having composite PN codes, there is provided a novel detecting and tracking circuit for faster acquisition of the component PN codes. The first component code of the received composite direct sequence spread spectrum code is noncoherently detected in a noncoherent detection branch and the subsequent component codes of the composite code are automatically detected in a coherent lock detection branch to provide faster acquisition than was heretofore possible. Further, while the noncoherent detection branch is acquiring the first component PN code, a novel coherent carrier tracking loop is acquiring and locking onto the direct sequence spread spectrum signal carrier.

Abstract: The present system is employed to generate and transmit information which is needed to construct or assemble truth tables and pertinent data which are directed to associated circuits which require testing. The present method employs a technique whereby information is nested, or compacted, in accordance with certain rules of grammar and is transmitted from a circuit design group to a vendor, i.e., a manufacturer of the circuit designed by a design group. When the nested information is expanded by a translator device, or by a translation program, at the manufactuer's location, it is directly expandable into truth table information for use by various logic testers. Each of the truth tables defines a specific function that the designer wants tested in the associated circuit. The manufacturer supplies the test platform hardware which generates the desired signal patterns defined by the truth table information and pertinent data.

Abstract: Apparatus for generating a complex composite code for fast acquisition by multiple access users is provided which comprises a composite code generator having an in-phase channel code generator and a quadrature channel code generator for generating two linear composite codes. The quadrature channel composite code is modulated onto a carrier which is 90.degree. out of phase with the in-phase carrier. The two linear composite codes are summed together and simultaneously transmitted to the receivers. Each receiver has a plurality of components code generators which generate replica component codes for fast acquisition of the composite code. A plurality of the components codes of the in-phase composite code are derived from the like components code generators in the quadrature channel to enhance speed of acquisition without acknowledgements by the receivers that any of the components codes have been acquired.

Abstract: A binary encoder for vector quantization is provided which comprises a plurality of identical two-level branch selectors connected in a turnaround cascade pipeline array. The upper levels of the two-level selectors are connected in series and the first selector receives a formatted digital data vector input. The upper level of last selector has its output connected to its own lower level input and the outputs of the lower level selectors are connected in series so that the last lower level selector in the turnaround cascade resides in the first two level selector. The output of the last lower level selector provides a desired compressed data vector output.