Abstract: A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block.

Abstract: An unsolicited dynamic interactive message is created wherein the message defines any graphical user interface elements to be displayed, the rules associated with the message, the appropriate methods and functions which can be performed and specific contextual interactions supported. The message definition can originate from a local or remote computer and can be pre and post processed as specified by the computing environment and the message definition itself.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of quest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.

Abstract: A method, apparatus and program product for focusing the display of tabular data wherein the display has multiple rows and columns of cells. A computer running a tabular data application includes a display for displaying the tabular data. The tabular data application includes a routine for defining a user defined area in the tabular data display in a focused display. The routine places indicators at the top, bottom, right side and left side of the focused display. The indicators may be one of an expand indicator or a collapse indicator. A movable cursor in the tabular data display is used to select at least one of the indicators for focusing the display. The routine in the tabular data application expands or collapses the display of tabular data to give a focused display. The expanding or collapsing of the display is determined by whether the selected indicator is an expand indicator or a collapse indicator.

Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

Abstract: Real-time statistical analysis is used to perform autonomic self-healing within the context of a 3-tier regression system for analysis of a computer system design component. Throughout the system, there are mechanisms for implementing self-healing if breakage is detected. The regression layer with the highest throughput is maintained in a much cleaner state than otherwise, thereby creating a more efficient environment for identifying and removing defects in the design.

Abstract: An apparatus, method and program product for providing dynamic visual cells in tabular data. A computer has an application for selecting a range of cells in said tabular data. A routine within the application recognizes a request for a graphical plot for data contained within the selected range of cells. The request may be from a user via a popup or a command menu. A routine within the application provides a graphical plot in a summary cell associated with the selected range of cells. The summary cell may be associated with the selected range of cells by being proximate the selected range of cells, or by location, color or a graphic property.

Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

Abstract: A method, system, method and computer program product for retrieving data. Records are retrieved from a hierarchical database. The records are categorized into a plurality of record types. Each record comprises a unique identifier field. A record map contains zero or more entries. Each entry comprises an identifying value, data from at least one record and a set of Boolean flags. Each flag corresponds to a record type. A computer iterates over the retrieved records. Data from each record is stored at an entry in the record map having an identifying value equal to the value included in the unique identifier field of the record. Moreover, the flag in this entry which corresponds to the record type of the record is set. Inner joins and outer joins are then performed using the contents of the record map.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced.

Abstract: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: Power consumption reduction of a mirrored RAID storage subsystems is disclosed, wherein data are mirrored to a secondary mirror disk system, the secondary mirror disk system alternates between an operational stage and a power-save stage, wherein data to be mirrored to the secondary mirror disk system is saved in a substantially always operational pre-stage storage if the secondary mirror disk system is in a power save stage and subsequently moved from the pre-stage storage to the secondary mirror disk system when the secondary mirror disk system is operational.

Abstract: A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Abstract: A system and program product having at least one subscriber subscribing to topics from one or more data sources. The number of subscriptions for each data source are registered in a table in real time. Upon detecting subscription activity, a matching routine compares the number of subscriptions registered for the available data source with a predetermined value, and if the number of subscribers exceeds the predetermined value a data source process corresponding to the data source will be started, and messages from the data source will be sent to the data source subscriber/s, otherwise, the data source provider will be stopped and not longer send messages.

Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.