Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

Abstract: A system and program product for enabling dormant computer hardware resources in a computer system having a set of dormant computer hardware resources. The method includes accepting a customer request to enable a set of dormant hardware resources, and providing computer readable instructions to a customer accessible console in communication with the computer system. The instructions are installable by the customer, and are capable of enabling dormant computer hardware resources upon installation. An order process establishes prerequisites, facilitates customer order placement, and provides rapid order fulfillment. Prerequisites include contract terms, information describing the computer system configuration, access to provider systems, and customer system setup. Ordering is facilitated through information management, configuration rules, and an interactive interface, presenting valid configuration options to the customer.

Abstract: What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

Abstract: What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.

Abstract: The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.

Abstract: A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the time that the cross-invalidate request is actually sent to the processors on a given node. If all of the remote nodes in the system indicate that the cross-invalidates could be sent during an initial directory snoop, the requesting node is able to return full exclusivity to a given cache line to a requesting processor at the time when it receives all of the partial responses, instead of having to wait for the final responses from each of the remote nodes within the system.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends.

Abstract: A tool assembly for removing an article from, or inserting an article onto, a printed circuit board which includes a tool housing having a handle portion and an article receiving portion, a plate slidable within the housing, the plate having a handle portion at a first end adjacent to the handle portion of the housing and two receiving portions at a second end, and two lever arms within the housing, each lever arm having a first end pinned to the housing and a second end of each lever arm inserted into the receiving portion of the plate such that each of the lever arms pivots about the pinned first end upon movement of the plate. The tool further comprises a pair of flexible rods located in respective recessed channels on either side of the article receiving portion, with one end of the flexible rods affixed to a first end of each of the lever arms, each of the flexible rods having a free end for interacting with an article retention device.

Abstract: Generating a unique URL key for a web document according to an obtained key generating policy. The URL of a web page is parsed according to the policy in order to generate the URL key. Preferably, the key generating policy is obtained from a well known source associated with the web page.

Abstract: Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.

Abstract: A wireless sensor network includes a controller connected with multiple antennas for sending out a beacon signal at different instants into different directions and for receiving a sensor signal. Furthermore, the wireless sensor network comprises a sensor having a receiver connected with a sensor antenna for receiving the beacon signal, a transmitter connected with the sensor antenna for sending out the sensor signal, and a control unit which takes care that the sensor signal is transmitted after the beacon signal has been received.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: The identity of the sender of an e-mail message is verified by performing a plurality of tests on DNS information. The DNS information is based on a client IP address or a sender address. Each test performed has a corresponding intrinsic confidence value representing the degree of confidence the test provides of the sender identity relationship. If multiple tests are successful the test result with the highest confidence value of the hierarchy of confidence values is used. The confidence value is optionally used in subsequent identity tests as specified by the subsequent test.

Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

Abstract: A provider server receives an order from a customer by way of a workstation for a customer selected configuration change of computing resources of an end user machine, the provider server having a predetermined time period and negotiates configuration change price for billing said customer for the purchase of said ordered customer selected configuration change, said negotiated configuration change price for billing said customer for the purchase of said ordered customer selected configuration change.

Abstract: Publishing electronic messages to clients within a group in a Pub/Sub message publishing environment wherein the group includes authorized participating clients in network communication with a pub/sub service. A client is authenticated for authority to publish messages to a selected group of subscribing clients.