Abstract: Disclosed is a method and apparatus providing the ability to create a multi-level prediction algorithm, whereby branch predictions beyond the first level of prediction are maintained at a secondary level because the prior level was unsuccessfully able to highly predict the direction of the stated branch accurately. A secondary level is smaller in size than the upper level through selected filtering thereby enabling high prediction accuracy of branches while minimizing the amount of hardware required to perform stated predictions.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.

Abstract: Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.

Abstract: In a network of computer systems having a group of users subscribing to a service comprising restricted channels, a user applies for an action to be performed by an automated software agent. The agent initiates a poll of a predetermined group of subscribers soliciting votes for approving the action. When the poll is complete, the votes are tallied by the agent and compared with predetermined authorization rules. If the votes pass the rules test, the action is approved and performed by a software agent. The user in one embodiment is an automated software agent.

Abstract: Electronic message response reception at a client computer in a conversation are throttled according to a predetermined critera in order to reduce the volume of messages the client is presented. Critera for throttling messages comprises only presenting messages in a predetermined time window, presenting only a predetermined number of response messages, presenting messages based on previous responder activity and presenting only messages from predefined senders.

Abstract: A method, system and program product is provided for dynamically integrating Backend System instances into a J2EE application server environment during runtime without having to restart the J2EE application server environment. The system comprises a deployment descriptor for deploying a J2C Connector into the J2EE application server environment and a Join/Leave manager. The manager implements an interface for detecting the Backend System instances, and an interface for providing access data and status information about the Backend System instances to the application. In addition, at least one node is enabled to run an application or its subcomponent for adding access data to, and deleting it from a storage media.

Abstract: A method is provided for recording a list of facilities available to a program executing on an information processing system. In such method a storage location and a length of data are defined for recording the list of facilities by a program being executed on the information processing system. An instruction is issued by the program for determining the available facilities and recording the list of available facilities in accordance with the defined storage location and data length. A processor executes the instruction to determine the available facilities and record the list of facilities in accordance with the defined storage location and defined data length. The recorded list of facilities can then be read by the first program.

Abstract: A method, system and computer program product for digesting data in storage of a computing environment. The digesting computes a condensed representation of a message or data stored in the computer storage. A COMPUTE INTERMEDIATE MESSAGE DIGEST (KIMD) and a COMPUTE LAST MESSAGE DIGEST (KLMD) instruction are disclosed which specify a unit of storage to be digested by a secure hashing algorithm.

Abstract: Electronic messages are published through a pub/sub service to subscribing clients. Client applications filter incoming messages according to user predefined criteria, only presenting messages to the user that pass filtering criteria. Messages are preferably Instant Messages transmitted in a SOAP protocol.

Abstract: A client subscribes to a pub/sub service, the client comprises an application program for performing an operation on a published message received from a Pub/Sub service. The operation on the message comprises any one of saving the message to storage, accessing a web service based on information in the received message, authorizing subscription, executing an application identified by the message, filtering the message information for presentation to a user, overriding a message function, transforming the message media format or forwarding the message to another node.

Abstract: A method, system and program product for executing a cipher message assist instruction in a computer system by specifying, via the cipher message assist instruction, either a capability query installed function or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.

Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).

Abstract: Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.

Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.

Abstract: The invention relates to a method and data processing system of managing a storage system, wherein the storage system comprises a first storage space and a second storage space, wherein the first storage space comprises a plurality of files, wherein for each file of said plurality of files at least one attribute is specified, and wherein a policy is assigned to each attribute. The method comprises the steps of determining a policy-specific probability distribution for each policy and of determining a policy-specific probability for each file by use of the policy-specific probability distribution. The method further comprises the step of determining a total probability for each file by use of each policy-specific probability and of moving each file of the plurality of files having a total probability equal to 1 from the first storage space to the second storage space.

Abstract: A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

Abstract: A method and apparatus enable supplementing a Branch Target Buffer (BTB) table with a recent entry queue that prevents unnecessary removal of valuable BTB table data of multiple entries for another entry. The recent entry queue detects when the startup latency of the BTB table prevents it from asynchronously aiding the microprocessor pipeline as designed for and thereby can delay the pipeline in the required situations such that the BTB table latency on startup can be overcome. The recent entry queue provides a quick access to BTB table entries that are accessed in a tight loop pattern where the throughput of the standalone BTB table cannot track the throughput of the microprocessor execution pipeline. By using the recent entry queue, the modified BTB table processes information at the rate of the execution pipeline which provides acceleration thereof.

Abstract: A computer Input/Output system having a fabric, a control unit (CU) and a host computer including a channel, the channel having a channel port connected by a first link to a channel neighbor port of the fabric, and the control unit having a CU port connected by a second link to a CU neighbor port on the fabric. Then an error is detected in the link or protocol between the channel and the control unit, error data are reported to the channel by the channel, the channel port, the channel neighbor port, the control unit, the CU port and the CU neighbor port and sent to the channel. The error data are provided to the host computer for analysis.

Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.