Abstract: A variable function system utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the system. The system also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, key input logic, data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. The read only memory may be programmed so that the system provides a variety of functions. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator semiconductor techniques.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from microcode store based on this macrocode word. In some machines, microcode for two states is fetched at one time, and then applied to the ALU register and bus controls in the next two successive cycles. In this manner, the microcode store can be the same as macrocode store.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc.. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur. A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface. This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral.

Abstract: A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

Abstract: An electronic digital processor system including an internal memory for the storage of data and commands, an arithmetic and logic unit, a register set, data paths and control/timing circuitry together with peripheral control circuitry which provides a number of memory configurations and also provides offset addressing capability to access the interrupt control circuitry, interval timing circuitry and input/output ports. The several memory configurations include configurations that allow for the storage of commands and the storage of data in external devices interfaced to the processor system through the input/output port circuitries.

Abstract: An MOS-type VLSI device is made by a process which provides a planar surface yet maintains geometric control for narrow line widths. The field oxide is recessed by etching the surface of a semiconductor body using thick masking for active device areas. Deposition of field oxide with poor step coverage allows the sidewall to be removed, leaving the top of the field oxide at the same level as the original silicon surface. The thick mask areas are lifted off, resulting in a planar oxide-insulated pattern for formation of transistors or N+ conductive lines.

Abstract: A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract: An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the internal mode, the data and the commands are stored in the internal memory. In the external mode, the commands which control the operations of the microcomputer are stored in the external memory. In the emulator mode, the user can combine the microcomputer with external devices to emulate a composite system with minimal hardware. The emulator mode would also allow the user to develop software for the composite system.

Abstract: A electronic digital processor system input/output circuitry including several input/output data ports where each port contains receiving circuitry to receive bit data from bit data pads and transmitting circuitry to transmit bit data to the data bit pads and control circuitry that provides for a configuration where one input/output port may respond to the address of another input/output port, allowing the second input/output port to perform other functions. This capability would allow a user to execute a program that emulates one configuration while the actual, physical connection of devices is, in fact, another configurations. The input/output circuitry also include control circuitry that determines whether the port is to receive bit data or to transmit bit data. This circuitry is connected to a data bus that couples the input/output data ports to the remaining electronic digital processor system.

Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern and means for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, and the pair of said submemory cells can store logic states opposite to each other.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, internal busses, address/data registers, an instruction register, and control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by control lines and a bidirectional multiplexed address/data bus. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM not in the main off-chip memory map) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.

Abstract: A microcomputer device is disclosed containing a read-only memory for programs, a read/write memory usually containing data, and a CPU, all in a single integrated circuit. The CPU is microprogrammed in that each instruction word fetched from the program memory initiates a sequence of microinstructions to perform the operation defined by the instruction word. The sequence is determined by addresses for a control ROM, and the addresses are selected by a method referred to as dispatching. The control ROM output includes a jump address by which the next address may be any location in the entire control ROM address range. Alternatively, the jump address may be modified by any one of several dispatches. A group dispatch selects one of the modes of accessing source and/or destination operands, based on one field of the instruction word. A subsequent function dispatch selects one of the set of available arithmetic/logic operations to be performed in the CPU based on another field of the instruction word.