Abstract: A microcomputer device is disclosed containing a read-only memory for programs, a read/write memory usually containing data, and a CPU, all in a single integrated circuit. The CPU is microprogrammed in that each instruction word fetched from the program memory initiates a sequence of microinstructions to perform the operation defined by the instruction word. The sequence is determined by addresses for a control ROM, and the addresses are selected by a method referred to as dispatching. The control ROM output includes a jump address by which the next address may be any location in the entire control ROM address range. Alternatively, the jump address may be modified by any one of several dispatches. A group dispatch selects one of the modes of accessing source and/or destination operands, based on one field of the instruction word. A subsequent function dispatch selects one of the set of available arithmetic/logic operations to be performed in the CPU based on another field of the instruction word.

Abstract: A microcomputer device is disclosed containing a read-only memory for programs, a read/write memory usually containing data, and a CPU, all in a single integrated circuit. The CPU is microprogammed in that each instruction word fetched from the program memory initiates a sequence of microinstructions to perform the operation defined by the instruction word. The sequence is determined by addresses for a control ROM, and the addresses are selected by a method referred to as dispatching. The control ROM output includes a jump address by which the next address may be any location in the entire control ROM address range. Alternatively, the jump address may be modified by any one of several dispatches. A group dispatch selects one of the modes of accessing source and/or destination operands, based on one field of the instruction word. A subsequent function dispatch selects one of the set of available arithmetic/logic operations to be performed in the CPU based on another field of the instruction word.

Abstract: An electrically programmable read only memory (EPROM) of the floating gate type is constructed having an improved coupling ratio made by allowing the edges of the floating gates to be self aligned with the edges of the control gates. The ratio of the capacitance between the floating gate and control gate is increased by extending the floating gate out over the source and drain.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU circuit is constructed to modify the carry-generate term so that the twos-complement function (and others) can be generated for either of the ALU inputs. By then connecting the most significant bit of the input to the arithmetic/logic control of the ALU, the absolute value function is generated. This results in faster signed multiply and divide instructions with less circuitry.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: Integrated circuit resistor elements which may be used as load devices in static MOS RAM cells are created vertically in polycrystalline silicon ion implanted to provide the desired resistivity. The method of making these devices is compatible with a standard self-aligned N-channel silicon-gate process. The cell size is reduced as the resistors can overly other elements, and an efficient layout provides a very small cell area.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction is executed in a sequence of microstates which are generated by selecting an entry point for the first address in a control ROM then continuing with a series of jumps and/or further entry points determined by the instruction and by the current state of the microprocessor. Improved circuitry is provided for selecting the entry point using a minimum of space on the chip by detecting the position of the leading 1 bit. Thus an instruction set can be used in which different groups of instructions have different numbers of leading zero bits.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The control ROM is an array of rows and columns of potential MOS transistors. This ROM is compressed by eliminating column lines which contain no transistors, and eliminating column decode circuitry associated with such column lines. The number of lines which can be eliminated is increased by reducing the number of row lines (thereby lengthening the row lines) and selecting default conditions of controls (by inverting some outputs) to increase the number of vacant positions in the ROM.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. A 16-bit device is shown as an example. The ALU and registers are laid out on the chip in a regular pattern with like bits in all registers and ALU aligned, and the busses are parallel metal strips overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses. A very dense layout results, saving space on the chip.

Abstract: A random access read/write MOS memory device or the like employs a delay circuit in clock generators to produce small increments of delay. The delay circuit consists of a field effect transistor connected as a transfer device with its gate precharged and the gate-to-source capacitance much larger than the parasitics of the gate node. A larger transistor may be connected to the output node to improve the output waveform by holding down the output voltage at the beginning of a cycle.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction word produces a sequence of microcodes which are generated by selecting an entry point for the first address of the control ROM then executing a series of jumps, depending upon the instruction. Usually operands must be fetched from memory and the result stored in memory. Operating speed is increased by fetching the next instruction and starting to generate operand addresses before the current result has been calculated and stored. The microprocessor can perform a memory access operation and an ALU operation in the same machine cycle.

Abstract: A fault tolerant memory device includes an array of rows and columns of dynamic random access memory cells and a set of EPROM cells of the floating gate type laid out with the same pitch, one aligned with each row, to store the identity of rows having bad cells. The EPROM cells are formed in preferred manner which permits them to be made with a standard N-channel process, and allows the row lines of the RAM and control gate connections to the EPROM cells to be of the same spacing.

Abstract: A non-volatile semiconductor integrated circuit has floating poly-silicon gates on the channel regions of memory cells. The information electronically stored in said floating gates is erased by the irradiation of an X-ray with predetermined amount. The writing step prior to X-ray irradiation causes the uniform erase of entire memory cells. The circuits other than memory cells are protected by a shielding coating against the X-ray irradiation.

Abstract: The characteristics of integrated circuits, such as the gate threshold voltage (Vtx) of insulated gate field effect transistors, or the current amplification factor (h.sub.FE) of bipolar transistors are altered by the irradiation of the X-ray with predetermined amount.The X-ray irradiation is used to make the integrated circuits with very accurate characteristics with high yield of production. It is also used to make variety of sample information by changing the characteristics of the same device one after another.

Abstract: A storage register which may be used to store several sets of data. The storage register may also be used as a demultiplexer to separate two or more sets of data that were received by the register over a single data line. The storage register includes a closed circuit loop of pairs of field effect devices and pairs of clocking devices wherein the clocking devices are coupled between the field effect devices. Input and output terminals are coupled to selected field effect devices. Embodiments of this storage register permit several bits of information to be stored simultaneously in the closed circuit loop and still remain accessible to input and output terminals at different times controlled by the clocking means. A further embodiment provides for several closed circuit loops to be arranged for the parallel storage of data bits.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. The ROM is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned. Address lines and gates are polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.

Abstract: A dynamic read/write memory cell of the one-transistor N-channel silicon gate type is made by a double-level polysilicon process in which the implant dosage is reduced for the channel stop regions beneath the field oxide. This causes the signal level on the bit lines to be improved, and also reduces leakage problems.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. To speed up the access time of the memory, the ground select is implemented and applied first, then the output of the ground select is used to generate the column select. In this manner, the biasing sequence for the array can begin before the decode of the column select has been completed.

Abstract: Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

Abstract: A static push-pull driver circuit employs an enhancement mode transistor and a low threshold "natural" transistor as its push-pull output, and two parallel gating transistors in the driver circuit for the low-threshold transistor. One of the gating transistors is also a low-threshold natural transistor, and the other is a much smaller depletion mode transistor. The depletion transistor may be formed in the channel area of the other gating transistor by an ion implant. The common gate of the two gating transistors is connected to a chip select signal.