Patents Represented by Attorney John G. Graham

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  • Programming sequence for electrically programmable memory
    Patent number: 4344154
    Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.
    Type: Grant
    Filed: February 4, 1980
    Date of Patent: August 10, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey M. Klaas, Paul A. Reed, Isam Rimawi
  • Display method for variable function programmed system
    Patent number: 4342094
    Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, data storage array, a decimal arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc., and to accommodate these different uses the output decoder is mask-programmable. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.
    Type: Grant
    Filed: January 12, 1979
    Date of Patent: July 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Gary W. Boone
  • Electrically erasable programmable MNOS read only memory
    Patent number: 4342099
    Abstract: An electrically programmable read only memory or EPROM is formed by an MNOS process compatible with N-channel silicon gate manufacturing methods. Row address lines and gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions formed beneath thin field oxide. Each storage cell is an MNOS transistor having an enhancement mode MOS transistor in series with it. The gates of the MNOS transistors are program address lines for programming and are formed by first level polycrystalline silicon. Each MNOS transistor in the array is programmed to be a logic "1" or "0" by proper voltages applied to row, output and program address lines to store charge at the oxide-nitride interface and thus change the threshold voltage for selected transistors. Then readout is provided using the MOS series transistors for access. A very dense array results.
    Type: Grant
    Filed: June 18, 1979
    Date of Patent: July 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Chang-Kiang Kuo
  • Implant programmable metal gate MOS read only memory
    Patent number: 4342100
    Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.
    Type: Grant
    Filed: January 19, 1981
    Date of Patent: July 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Chang-Kiang Kuo
  • Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM
    Patent number: 4339766
    Abstract: An MOS/LSI type dynamic RAM with single 5V supply and grounded substrate employs a pair of dummy columns on each end of the cell array to prevent pattern sensitivity in testing. The dummy columns have capacitors which alternate between large and small so a given cell will always read a "1" or "0" upon refresh. These cells are not accessed in normal read or write cycles. Thus, regardless of the row addressed, one column line half on each side will go high and the other low. This shields the ends of the array from diffusing electrons (minority carriers).
    Type: Grant
    Filed: October 11, 1979
    Date of Patent: July 13, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: G. R. Mohan Rao
  • Method of making implant programmable N-channel read only memory
    Patent number: 4336647
    Abstract: An MOS read only memory or ROM formed by the standard N-channel silicon gate manufacturing process uses a cell structure which allows implant programming after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon strips and output and ground lines are metal strips perpendicular to the address lines; these metal strips make contact to the sources and drains defined by N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by selective ion implant through the polysilicon gates and thin gate oxide, using photoresist as a mask, after application of the metal level. The ion implant is not required to penetrate through the metal lines.
    Type: Grant
    Filed: December 21, 1979
    Date of Patent: June 29, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Semiconductor memory cell with clocked voltage supply from data lines
    Patent number: 4334293
    Abstract: An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. The coupling transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.
    Type: Grant
    Filed: May 12, 1980
    Date of Patent: June 8, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: James E. Ponder
  • N-Channel MOS comparator
    Patent number: 4333025
    Abstract: A voltage comparator circuit suitable for a semiconductor integrated circuit device comprised of a variable impedance being controlled by input voltages that are to be compared with one another and a feedback circuit comprised of a pair of cross-coupled transistors each having a gain of unity to provide a differential signal of infinite gain to a single ended output circuit.
    Type: Grant
    Filed: March 13, 1978
    Date of Patent: June 1, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: John C. Domogalla
  • Dynamic memory with on-chip refresh invisible to CPU
    Patent number: 4333167
    Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.
    Type: Grant
    Filed: October 5, 1979
    Date of Patent: June 1, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Semiconductor read/write memory array having serial access
    Patent number: 4330852
    Abstract: A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: May 18, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: Donald J. Redwine, Lionel S. White, Jr., G. R. Mohan Rao
  • Dynamic decoder input for semiconductor memory
    Patent number: 4330851
    Abstract: A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.
    Type: Grant
    Filed: March 21, 1980
    Date of Patent: May 18, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Lionel S. White, Jr.
  • High density read/write memory cell
    Patent number: 4328510
    Abstract: A semiconductor memory cell of the random access, read/write type includes a single combined storage capacitor and access transistor structure. The process for making the cell is compatible with the standard method of making N-channel silicon gate MOS integrated circuits. A thin epitaxial region is grown over an implanted isolating region and a heavily doped bit line in each cell area. A thin gate oxide over the epitaxial layer separates it from a metal address line. A very small cell size is provided.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: May 4, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: G. R. Mohan Rao
  • Method of making a contact programmable double level polysilicon MOS read only memory
    Patent number: 4326329
    Abstract: A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.
    Type: Grant
    Filed: February 28, 1980
    Date of Patent: April 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • High coupling ratio electrically programmable ROM
    Patent number: 4326331
    Abstract: An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a process which allows the edges of the floating gates to be self-aligned with the edges of the control gates. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased by extending the floating gate out over the source and drain since the thick oxide reduces coupling from the floating gate to the source and drain.
    Type: Grant
    Filed: September 17, 1979
    Date of Patent: April 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Daniel C. Guterman
  • Column decoder discharge for semiconductor memory
    Patent number: 4327426
    Abstract: A random access read/write MOS memory device employs an array of rows and columns of memory cells which are accessed by an address input applied to row and column decoders. To avoid unwanted trapping of voltages on unselected column decoder outputs, the circuitry of the invention provides positive discharge of nodes which should not maintain voltage thereon.
    Type: Grant
    Filed: February 11, 1980
    Date of Patent: April 27, 1982
    Assignee: Texas Instruments, Incorporated
    Inventor: Hugh P. McAdams
  • Method of making CMOS device allowing three-level interconnects
    Patent number: 4325169
    Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.
    Type: Grant
    Filed: October 11, 1979
    Date of Patent: April 20, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: James E. Ponder, Graham S. Tubbs, Perry W. Lou, Stephen A. Farnow
  • Variable function programmed calculator
    Patent number: 4326265
    Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, data storage array, a decimal arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc., and to accommodate these different uses the output decoder is mask-programmable. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.
    Type: Grant
    Filed: January 12, 1979
    Date of Patent: April 20, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Gary W. Boone
  • Static random access memory with merged bit lines
    Patent number: 4322824
    Abstract: A static Random-Access-Memory having a single bit line between each pair of adjacent columns of memory cells, implemented in a self-aligned, N-channel, silicon-gate system. Resistor element load devices are made in second-level polycrystalline silicon by an ion implant step. The second-level polycrystalline silicon is insulated from the first-level polycrystalline silicon by a multiple oxide insulation layer. An additional word line for each row of memory cells provides differentiation between adjacent memory cells sharing a single bit line.
    Type: Grant
    Filed: November 13, 1979
    Date of Patent: March 30, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: James D. Allan
  • High speed serial shift register for MOS integrated circuit
    Patent number: 4322635
    Abstract: A semiconductor device of the MOS/LSI type uses a high speed serial shift register in its input/output system. In a memory device, the serial shift register has a number of stages equal to the number of columns in the memory cell array and is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: March 30, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Donald J. Redwine
  • High density VMOS electrically programmable ROM
    Patent number: 4322822
    Abstract: An electrically programmable memory array is made by a process in which the memory elements are capacitor devices formed in anisotropically etched V-grooves to provide enhanced dielectric breakdown at the apex of the groove. After breakdown, a cell exhibits a low resistance to a grounded substrate. Access transistors in series with the memory elements have control gates which also form address lines. The oxide thickness in the V-groove may be thinner than the gate oxide thickness for the access transistor providing a lower programming voltage. These factors provide a very small high speed device.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: March 30, 1982
    Inventor: Roger K. McPherson