Abstract: A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by two address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming.

Abstract: An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on a large, low-resistance transistor which is in series with the voltage supply line going to all of the other electronic circuitry on the chip.

Abstract: A charge pump circuit for generating a substrate bias for MOS/LSI integrated circuit chips is provided, preferably for P-channel integrated circuits. The charge pump circuit includes an osicllator producing a square wave which is applied to a reference circuit that is also responsive to a threshold voltage Vt monitor. The reference circuit applies to a pump diode a square wave having a level responsive to the supply and thresholds. A zero voltage drop source follower connects the square wave to the diode to avoid loading. The threshold monitor forces the square wave to a high level when the threshold is below a certain value.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by row address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon.

Abstract: A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.

Abstract: A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: A simplified protective system as for a home burglar alarm comprises a beam generator such as a solid state microwave module along with a detector and alarm or indicator. The beam generator and detector unit is positioned along a line-of-sight normal to a window or other object being monitored. A reflector such as a mirror on the window reflects the beam back to the detector. When the window is moved or broken, the beam does not reach the detector and the alarm is actuated.

Abstract: An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on an oscillator, the output of which is pumped up to a level above the battery, and the high level voltage is used to drive a large, low-resistance transistor. This transistor is in series with the voltage supply line going to all of the other electronic circuitry on the chip. The oscillator and pump circuit assure that the drop across the transistor is negligible.

Abstract: A detector circuit for MOS/LSI integrated circuit devices comprises a series transistor which has a sense clock applied to its gate and a gated capacitor connected between the gate and a sense node. The sense node and an input node may be precharged to a level at or near the supply. During the sense clock, the input and sense nodes are shunted together by the series transistor. If at the logic level of the supply, the gated capacitor is off and does not affect the circuit; if the input node decays toward the other logic level, the gated capacitor is on and the trailing edge of the sense clock causes the sense node to be switched to a full logic level.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

Abstract: A digital processor which may be used in a calculator or the like is provided by an MOS/LSI semiconductor chip which contains a ROM or read-only-memory for storing instructions, a bit-parallel arithmetic unit for operating on data stored in a random access memory and control circuitry for defining the operation of the system. The control circuitry includes a programmable logic array for decoding instruction words. Space on the chip is saved by a time-shared decoder which forms part of the programmable logic array and also decodes addresses for the ROM.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: An electronic digital processor is disclosed of the type used in miniature calculators. The processor is fabricated as a single MOS-LSI semiconductor chip and includes a large read-only-memory or ROM for storing instruction codes, along with addressing circuitry for generating addresses for the ROM by either sequencing a program counter or by branching to an address contained in a branch instruction code. At the same time as a branch instruction is implemented, parts of the instruction code used for the branch address may be employed as an op code to perform operations within the processor.

Abstract: A self-refresh MOS RAM cell uses a resistor element made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor element is beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. The cell employs two transistors and a gated capacitor, connected in a manner such that a stored "1" switches the implanted resistor to a high impedance state, while a stored "0" maintains the resistor in a relatively low resistance state.

Abstract: A source follower circuit which exhibits essentially zero input to output voltage drop and very low capacitive loading on the input. A current mirror arrangement is used. The input is connected to the gate of a depletion mode transistor which is connected in series with an enhancement mode device. The gate of the enhancement device is biased by a series circuit having a depletion device with gate shorted to source and an enhancement device with gate shorted to drain.

Abstract: An electronic digital processor which may be used in a hand-held calculator is implemented in a single MOS/LSI semiconductor chip. The processor includes a ROM for storing instruction codes, a RAM for storing data, an arithmetic unit for performing operations on data under control of micro-instructions or commands, and control circuitry including a decoder for generating the commands in response to the instruction codes. The arithmetic unit is controlled by a group of micro-instructions generated from a certain class of instruction codes, while another class of instruction codes includes fields for constants used in some operations such as "compare contents of accumulator with a constant.