Abstract: A semiconductive device and a method for producing the semiconductive device, wherein random defects or inaccuracies in precise registrations of certain patterns are compensated by the introduction of selected impurities. The selected impurities bring about changes in the electrical characteristics of those portions of the semiconductor affected by the random defects or registration inaccuracies so as to prevent them from causing malfunctions in the completed devices.

Abstract: N-channel silicon gate MOS memory cells are programmed by an ion implant step which is done prior to forming the gates or the diffused source and drain regions. The implanted devices have a threshold voltage which is about zero, so the devices cannot be turned off at usual logic levels. Either ROM or RAM arrays can be made using implant for programming.

Abstract: An improved method of making N-channel, silicon gate, MOS integrated circuits such as used for memories is disclosed. Structural damage to the crystalline silicon such as caused by an ion implant process is reduced by a high temperature treatment in an inert atmosphere followed by oxidation. This treatment also alters the concentration profile of the implanted impurity to provide improved device characteristics.

Abstract: A random access memory device of the MOS integrated circuit type using an array of one-transistor storage cells employs bistable sense amplifier circuits, one located in the center of each column line. The bistable circuits have current-limiting control devices in series therewith and the control devices are selected by the address circuits in a manner such that during an initial sensing period the current is low, then during a later period more current may be permitted for a higher level output. In parts of the array which are not being accessed by the current address, the increased current level is not permitted, thus reducing power dissipation.

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes, on a single chip, an arithmetic logic unit (ALU), an instruction register, a random access memory and a control system. Interconnection of the functional elements of the CPU is accomplished via sequential use of a common parallel buss. The ALU contains precharged parity and carry propagate circuits which enhance circuit speed. The precharged circuits are formed using conventional insulated-gate-field-effect transistor fabrication techniques.

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine cycle one digit of the RAM is accessed. Also, in a machine cycle the ROM is addressed to provide an instruction word, and the word is decoded and executed. A unique five phase clocking arrangement is used which permits the complex operations to be implemented within a machine cycle.

Abstract: Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data memory, an arithmetic unit for executing operations on data, and a control arrangement for defining the functioning of the machine including a ROM for storing a large number of instruction words, and control decoders for receiving instruction words from the ROM and producing various commands for the control arrangement. Separate X and Y address registers are provided for selecting the location in the ROM for the next instruction. Input and output terminals are provided, as for keyboard input, and display output. A test mode of operation is provided for quality control upon completion of manufacture of the chip.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a machine cycle one digit of the RAM is accessed, and also the ROM is addressed to provide an instruction word which is decoded and executed. The data input to the system is by four parallel lines which may be connected to a scanned keyswitch matrix or to BCD or binary data sources. Within the chip, the data inputs may be coupled to the input of the arithmetic unit, or to the data memory directly.

Abstract: A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save space on the chip by employing a virtual ground feature and to operate fast due to a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line and to an output line, using a minimum number of transistors. The Y lines are precharged to a value significantly less than the chip supply voltage, so that operating speed is enhanced.

Abstract: A multiplexed system for displaying characters as in an electronic calculator, wherein the display is of the segemented type, typically employing visible light emitting diodes. Instead of actuating the digits or characters of the display in sequence while selectively actuating the segments of the display, the segments are scanned in a regular sequence while the digits are selectively actuated in a code corresponding to the data to be displayed. This system permits the construction of a calculator in which the display is driven directly from an MOS/LSI calculator chip without using digit and segment drivers.

Abstract: A method for displaying characters using a segment scanning technique, as for an electronic calculator of the type employing segmented visible light emitting diodes. The segments are scanned in a regular sequence while the digits are selectively actuated in a code corresponding to the data to be displayed. A representation of each segment to be displayed is compared with each of the digits in a data memory, and a display signal is generated if the digit contains each segment. These display signals are used to control the selective actuation of the digits.

Abstract: The disclosure relates to methods of forming Insulated Gate Field Effect transistors and the product suitable for integrated circuits with channel lengths of 1 micron or less, the transistors being isolated from other transistors or other components in the circuit without the requirements of extra isolation steps. This is provided by means of a double diffusion which isolates the channel of the transistor from other elements in the circuit. Channel length is solely a function of the diffusion schedule through openings in the oxide through which the double diffusion takes place.

Abstract: An integrated injection logic memory cell includes a latch circuit for holding a binary bit of information. Circuits are provided to maintain current injection into the latch circuit at all times, including during the reading and writing operations. The latch circuit is made up of a pair of cross coupled vertical, inverted transistors. The circuits for maintaining the injection current into the latch are made up of lateral transistors selectivity coupled to a memory access control circuit for supplying bi-level signals through word and column select lines.

Abstract: An electronic calculator or data processing system implemented on semi-conductor chips to operate several chips in synchronism where at least one element common to the operation of all chips is responsive to sequentially generated operating states.A master clock applies clock pulses to the clock input terminal of one chip.A control gate is provided in the circuit leading to the clock input terminals of the other chip or chips.A comparator is connected to selected operating state output terminals from both or all of said chips and is connected to the control gate for inhibiting flow of clock signals to the other chip or chips so long as said selected states differ.

Abstract: A system for detecting intruders in a building, using sets of light emitters and detectors. Interruption of a beam between an emitter and a detector produces a radio signal picked up by a control console. The system is easily installed because the emitters and detectors are battery powered, requiring no connection to house wiring, and the radio link between detectors and the control console avoids wiring for the signal circuit.

Abstract: A computing system includes a central processor unit (CPU) integrated on a monolithic chip, in combination with a plurality of external memory units. The CPU includes a parallel arithmetic logic unit (ALU) and an internal random access memory interconnected on a common parallel bus with an instruction register. The random access memory defines the general purpose data registers, program and memory address registers, and a multilevel program address stack. Timing circuitry in the CPU enables utilization of either serial or random access external memory units. The timing control of the CPU enables a method of operation characterized by sequential transmission of low order address bits, WRITE data, high order address bits and READ data over a common external parallel bus that interconnects the CPU with the external memory.

Abstract: A memory cell comprising field effect transistors for use in a random access memory array. The cell is of the dynamic type wherein data is stored on capacitive elements, and is self-refreshing; no circuitry external to the array is needed for refresh, other than clock sources. Five MOS field effect transistors are employed, with two non-overlapping clocks, a data buss for each row of the array and one address line for each column. The transistors and associated capacitors are arranged to reinforce a stored "1" or "0".

Abstract: Control of a drum printer by signals from an LSI/MOS calculator chip. Drum generated signals and control signals generated on a second LSI/MOS chip operating in synchronism with the calculator chip selectively provide for actuation of a line of print hammers.Further, two channels coupling the calculator chip to the control chip provide for flow of coded character words and function words for printing of both functions and characters on a given line.Further, control of the printer is accomplished by observing which digit time in the calculator chip a specific dedicated flag is set.