Abstract: A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.

Abstract: An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Abstract: An array of rows and columns of memory cells of the virtual ground type employs a cell layout which has one column line per column instead of requiring extra lines for ground. Half of the column lines are used as outputs and half as ground. One output line and one ground line are selected by improved decode circuitry. The cell array is of a continuous web type wherein metal-to-silicon contacts are shared by four adjacent cells.

Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "O's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Abstract: An insulated gate field effect transistor has channel stop regions which are separated from the heavily doped drain region so that the sidewall or drain/source to channel stop capacitance is reduced. This is accomplished by a buried outdiffused channel region which also functions as the channel stop in a VMOS transistor.

Abstract: A calculator anti-theft system for preventing theft of small, personal electronic calculators comprises a keyboard, a display, a calculator device, and means to store an anti-theft code individual to each calculator. The anti-theft code may be stored within the calculator device or may be stored in an external device. The calculator device is programmed to compare a specified number of the keyboard entries immediately following power-on to the individual stored anti-theft code. If the initial keyboard entries match the anti-theft code, the calculator is enabled, and normal operation is possible. If these first entries do not match the code, the display, the keyboard, or the calculator itself is disabled to prevent normal calculation. In other embodiments, comparison of the stored anti-theft code to the initial keyboard entries is made in a device external to the device which performs the normal calculation functions.

Abstract: A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application of high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. An over-erase sensor transistor separate from the memory transistor prevents the floating gate from being discharged below a point where the memory transistor will be depletion mode.

Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates, and electrically erased power voltages applied to the source, drain, control gate and substrate. The floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming by allowing the transistor created by the floating gate to go into the depletion mode. The threshold of this series enhancement transistor is lowered by an implant step in the process which is self-aligning.

Abstract: A semiconductor integrated circuit such as an MOS random access memory or RAM is made by standard N-channel silicon gate manufacturing methods but using positive photoresist for successive masking steps by re-exposure of the photoresist. In making ion implants for threshold adjustment, the positive photoresist is deposited and exposed using a first mask which defines the channel areas of transistors which are to have one threshold voltage; upon developing, the channel areas will be bare so a first implant will penetrate only these channel areas. Then, without stripping the photoresist, another exposure using a second mask defines the channel areas of transistors which are to have another threshold voltage. After the photoresist is developed a second time, another implant will penetrate the channel areas defined by the second mask as well as the first.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine cycle one digit of the RAM is accessed. Also, in a machine cycle the ROM is addressed to provide an instruction word, and the word is decoded and executed. A unique five phase clocking arrangement is used which permits the complex operations to be implemented within a machine cycle.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit of the dynamic type at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. A coupling transistor connects each column line half to one of the cross-coupled driver transistors of the bistable circuit. The coupling transistors are of the depletion mode type and each has its gate connected to the sense node on the opposite side between the other coupling transistor and driver transistor.

Abstract: An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.

Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor elements are beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. Resistors of this type are ideally suited for load devices in static RAM cells.

Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors and a pair of access transistors along with load devices which are punch-through elements resembling short channel MOS transistors without gates. The punch-through elements each have an electrode integral with the drain of one of the driver transistors, and another electrode coupled to a voltage supply. A cell layout of very small size is possible.

Abstract: A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.

Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors which are formed by a method which results in field oxide over the source and drain regions of the MOS transistors. Access transistors are formed by a different method and have silicon gates self-aligned with their source and drain diffusions. The load devices are punch-through elements resembling short channel transistors without gates. These features permit a cell layout with a minimum of space used for the cross-coupling connections, and the polysilicon address line can cross over the ground line, producing a very small cell size.

Abstract: A semiconductor memory of the static type employs a pair of cross-coupled driver transistors which are formed by a method which results in field oxide over the source and drain regions. Access transistors are formed by a different method and have silicon gates self-aligned with their source and drain diffusions. The load devices are ion-implanted polycrystalline silicon strips which overlie the driver transistors. These features permit a very small cell layout with a minimum of space used for the cross-coupling connections, and the polysilicon address line can cross over the ground line.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also incudes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal insulator-semiconductor techniques.