Abstract: A phase transition detector for PSK signals which utilizes a dual channel SAW differential delay line to achieve a required delay. Each channel or path of the SAW device comprises an input and an output transducer. The two channels provide a predetermined differential delay (T) inasmuch as they are of different lengths. A PSK input signal is delivered to a power splitter, with the output therefrom coupled to the pair of input transducers of the SAW device. The output transducers are coupled to a multiplier which serves to detect phase transitions in the input PSK signal. The multiplier output is coupled to an output terminal via a low pass filter which provides harmonic repression. In another embodiment a SAW device comprises a bank of dual channel differential delay lines with each dual channel set to a different predetermined delay (T) so that a plurality of PSK signals of different chip rates can be separated out and detected.

Abstract: The disclosure relates to error/fault detection in signal processing systems such as those employed in a time division multiplex conferencer. The digital message samples (of the conferees) and the accompanying parity bits are delivered to a signal processor e.g., a binary arithmetic adder (10). The adder sums the message samples and this sum is coupled to a first parity tree (11), which in response thereto generates a first parity bit. The carries generated by the summing operation and coupled to a second parity tree (12) along with the message parity bits and the second parity tree generates a second parity bit therefrom. The first and second parity bits are compared (13) and if they differ a fault exists. Corrective action is taken immediately--the faulty conference "leg" is removed from the conference connection without affecting the remaining legs in the conference or any other conference.

Abstract: A dual-clock, edge triggered, flip-flop circuit wherein one set of outputs responds to two independent inputs without giving rise to indeterminate states regardless of the combination of inputs comprising a first pair of gates (1-2 or 11-12) cross-coupled to form a first trigger flip-flop. A second pair of gates (7-8 or 17-18) are cross-coupled to form a second trigger flip-flop. A third pair of gates (4-5 or 14-15) are cross-coupled to form an output flip-flop having set and reset terminals and a pair of output terminals. A gate (3 or 13) is coupled from the output of the first trigger flip-flop to the set terminal of the output flip-flop, the input to the first trigger flip-flop also being coupled to the input of this latter gate. Another gate (6 or 16) is coupled from the output of the second trigger flip-flop to the reset terminal of the output flip-flop, the input to the second trigger flip-flop also being coupled to the input of this gate.

Abstract: A time division multiplex conferencer for continuously summing and outputting digital message samples received from n subscribers in n respective time slots. Message samples collected from each subscriber of a conference connection are summed during a first time frame and outputted during a second time frame. The conferencing is carried out in real time under common control to provide one or more conference-type connections between two or more subscribers. The conferencer also has the ability to establish transmit-only or receive-only connections for one or more subscribers. The conferencing is conducted in a manner that is completely independent of time slot assignments within a frame.

Abstract: A driver circuit turns an LED `on` and `off` in response to input logic `one` and `zero` data signals. A current regulator 11 is series coupled with the LED and serves to maintain a constant current to the LED over time, temperature, and supply voltage variations. During turn-off, this current is shunted away from the LED by a low impedance emitter follower (Q3), operated in the active non-saturated region, and a small reverse bias potential is momentarily applied to the LED which quickly sweeps out the charge stored in the LED junction. At the end of the `off` cycle there is a forward prebias potential across the LED. During turn-on, the current shunt is reverse biased and a current peaking circuit (14) provides a momentary additional current through the LED. This instantaneous forward current peaking and the forward prebias both serve to substantially reduce the turn-on delay and rise time of the optical drive signal.

Abstract: A binary full adder, including provision for carry digits, is implemented using metal-oxide semiconductor field-effect transistors (MOSFET) in the exclusive-OR configuration. The improved structure realizes economies in space occupancy, and device topology, reduction in power requirement and no loss in propagation time over prior full adders employing conventional logic structures.

Abstract: A single-sideband FM receiver comprises an input (RF) stage (13), a mixer (14), a local oscillator (15) an intermediate frequency (IF) amplifier (16), and an FM detector (18). An oscillator (17) is phase and frequency locked to the IF frequency. The output of this phase-locked oscillator is coupled to the FM detector via a bandpass filter (20) and an amplitude control circuit (19), which controls the level of the signal delivered to the FM detector (18). In the detector (18), the output of the phase-locked oscillator (17) adds a component which is equivalent in phase and frequency to the carrier term received from the IF amplifier (16). This feed-forward signal from the phase-locked oscillator reduces harmonic distortion.

Abstract: A bit compression multiplexer (FIG. 2) for a pair of time division multiplexed digital bit streams each one of which includes a plurality of PCM encoded signals deposited in separate and distinct channels of a repetitive frame and signaling bits multiplexed therewith. The PCM encoded signals of successive frames are normally bit compressed (23) into n-bit signals, but periodically the encoded signals of a frame are bit compressed into n-1 bit signals. The bit compressed signals of the pair of bit streams are time division multiplexed (24) with each other, with the multiplexed compressed signals occupying separate and distinct channels of a repetitive frame. The signaling bits are extracted (21) from the pair of digital bit streams and are inserted (24) into predetermined n-1 bit channels of the last-recited repetitive frame. The signaling bits that are placed in a given channel are related to the encoded message signal of that channel.

Abstract: A bit compression coding circuit incorporates signaling bit insertion. An input signal sample(s) representing, for example, PCM encoded speech or voiceband data, is delivered to a difference circuit (31) where a predicted signal (s.sub.e) is subtracted from it. The predicted signal is an estimate of the input sample derived from a predictor (32). The resultant difference signal is coupled to the input of an adaptive quantizer (34) which provides at its output a bit compressed quantized differential PCM version of the difference signal. A multiplexer (37) receives the output of the quantizer and serves to periodically preempt the least significant bit of the bit compressed PCM signal and substitute a signaling bit therefor. The output of the multiplexer is coupled to the input of an adder (38) wherein it is added to the predicted signal.

Abstract: A differential pulse code modulation system is made adaptive to quantization noise in a way which permits variable-rate operation as either a conventional R-bit embedded code or as a combination of a conventional R-bit code and a further explicit noise code with instantaneous quantization. Additional improvement in signal-to-noise ratio is attainable by using a noninstantaneous variable-bit allocation procedure for equal-length sampling blocks with an averaged fixed bit code.

Abstract: A relay load is connected in the collector path of a first transistor (Q1) of high current carrying capacity. A second transistor (Q2) of similar conductivity type is effectively coupled across the first transistor. The bases of said first and second transistors are connected together. A current mirror circuit (Q3-Q6) is coupled from the collector of said second transistor to said bases to provide the additional base drive necessary to drive the first transistor towards saturation regardless of its Beta when maximum load current is required. The mirror circuit is designed so that the effects of transistor V.sub.be mismatches in the mirror are minimized.

Abstract: A telephone line circuit comprises a transformer that has a primary (13) and a secondary (14) winding. A low resistance (15) is connected in series with the primary winding. An amplifier circuit (17) is coupled across the resistance and serves to develop a predetermined dc control voltage. This control voltage is used to establish a dc current flow in the secondary which is n times that of any dc current flow in the primary, where n is the transformer turns ratio. The dc current flow established in the secondary is in a direction opposite that of the dc current flow in the primary. A second amplifier circuit (31, 36, 23) is coupled across the primary winding and serves to generate an ac control signal which is also delivered to the secondary winding to create a predetermined ac termination impedance.

Abstract: A method for analysis of rotary dial pulses focuses on transitions between pulse levels and differentiates true level changes from noise using a procedure employing two sample counters. One counter registers the number of consecutive samples at either the high or low levels and, once a predetermined number of consecutive samples are detected, a corresponding high or low level is declared. However, since noise may influence the detection, the total number of samples, from the first indication of a level change until the declaration of a state, is maintained in a second counter. A false transition reinitializes both counters, while level changes yielding less than the predetermined number only reinitialize the first counter.

Abstract: An improved transimpedance amplifier allows an optical transmitter and receiver to be in close proximity to each other without fear of overloading the receiver. The improvement increases the dynamic range of the transimpedance amplifier and thereby the operating range of the receiver. A peak detector (22) at the output of an inverting amplifier (11) within the transimpedance amplifier turns on a field effect transistor (FET) circuit (23) when an AC component of an electrical signal becomes so large that the inverting amplifier would otherwise go into saturation. The FET circuit (23) acts as an AC shunt impedance at the input of the inverting amplifier and diverts the excess AC current to ground (30). Also, the FET circuit (23) acts as a DC resistance in concert with sense and sink current mirrors (21) and (24) to effectively divert an excessive DC component of the electrical signal away from the input of the inverting amplifier (11).

Abstract: A technique for maintaining frame synchronization in a OAM system transmitting nondifferentially encoded data is disclosed. In accordance with the present invention, multibit words (F.sub.I, F.sub.Q) comprising framing bits are formed and inserted into the transmitter data channels. The value of the framing bit is insensitive to the rotational effects of phase ambiguity by having a predetermined value and by being inserted within a predetermined bit position in each data channel. In the disclosed embodiments, regeneration errors can also be corrected by the transmission of predetermined quadrant bits within the multibit words. In addition, the spectral tones generated by multibit word transmission can be reduced by the use of utility bits in the multibit words.

Abstract: An encoder (100) for processing an input signal to produce a ternary coded data stream having supressed DC comprises circuitry, and its associated methodology, including an arrangement (120,130,150) for augmenting the data stream with a compensating set of code symbols as determined by the number of positive and negative code symbols in the data stream as well as all prior compensating code symbols. A decoder (200) processes the received signal to extract the symbols in the data stream corresponding to the input signal. In order to achieve a preselected end-to-end transmission rate with the encoder-decoder combination, the rate of the signal propagated between encoder and decoder is increased to compensate for the appended code symbols.

Abstract: A majority vote circuit determines when the majority of a group of signaling channels is properly conveying a common message in conjunction with a status signal individual to each channel. Respective status and message signals from each channel are scanned in pairs and in sequence. The number of valid message and status signals are accumulated in separate counters. A comparison circuit triggered by the completion of a scanning sequence matches counter outputs stage by stage to determine whether or not the count level in the message signal counter exceeds by one-half the count level in the status signal counter as an indication that a majority of a variable majority of the working channels conveys the same message signal.

Abstract: The disclosed operational amplifier comprises a first pair of complementary type transistors that have their emitter-collector paths connected in series across a source of reference potential. The emitters of the transistors are connected together and to an output terminal. A feedback resistance is coupled from the output terminal to the amplifier input. A second pair of complementary type transistors are similarly connected across said reference potential, with the emitters thereof connected together and to a second output terminal. A second feedback resistance is coupled from the second output to the amplifier input. A pair of resistors of predetermined values are respectively connected between the base electrodes of similar type transistors of the first and second transistor pairs. And a pair of constant current sources are respectively coupled to the base electrodes of the second pair of transistors.

Abstract: Random beam positioning for an E-scan radar system having an electronically teerable antenna is controlled by a digital computer which is programmed to generate lists or files of portions of the desired area of surveillance. Two separate lists are generated corresponding to the forward and rear postions of the area of coverage. These lists are thereafter independently randomized and combined to generate beam position commands for the desired surveillance region, thereby providing full radar coverage over a desired region while decreasing the probability of being tracked by an undesired detector.

Abstract: Beam pointing errors and sidelobes resulting from temperature variations on he aperture and power divider of a series phased array antenna operating at a plurality of selected operating channel frequencies and having uniformly spaced elements are compensated for by placing a temperature sensor on both the aperture and power divider and converting the respective temperature outputs to digital signals which are fed to a digital beam steering unit. A pair of programmed memories are included in the beam steering unit which respond to an address or pointer corresponding to the digitized temperature values and the selected operating frequency to read out stored digitized beam steering phase gradients and feed phase corrections which are combined and sequentially applied at regular intervals to symmetrically located phase shifter pairs. A uniformly compensated beam is thereafter radiated at a predetermined phase angle.