Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives and stores the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's storage subsystem receives and stores the generated information from control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module.

Abstract: A digital data storage subsystem stores data for use by digital data utilization device. The data as used by the digital data utilization device being organized in the form of variable-length records. The digital data storage subsystem includes a digital data storage device, a cache and a cache control. The digital data storage device has at least one fixed block storage unit for storing a predetermined amount of data, the storage unit storing at least one record and additional padding if the record does not comprise at least said predetermined amount of data. The cache including at least one cache slot which can accommodate the storage of the predetermined amount of data, that is, the amount which can be stored on the block storage unit of the digital data storage device.

Abstract: A reduce cross-talk wiring harness and method for accomplishing same. The wiring harness is used for routing signals from a bus and tag housing to a controller, and for routing signals back from the controller to terminators in the bus and tag housing. The harness includes an input pair and an output pair of bus and tag ribbon cables. The cables in each pair are of essentially the same length. Each pair has a combined bus and tag connector attached to one end, and individual bus and tag connectors attached to the other end. The input and output bus and tag ribbon cables are grouped together for at least part of the distance between the controller and the bus and tag housing in such a manner that at least one of both bus cables or both tag cables are adjacent one another, to reduce cross-talk between the bus cable of one cable pair and the tag cable of the other cable pair.

Abstract: Two data communication channels having electrical ground positions that alternate with control and data positions are terminated in a single, dual-channel connector that occupies generally the same interconnection board real estate as is required for a single, prior art, data communication SI connector, such as for a Small Computer System Interface (SCSI) communication channels. A two-channel SCSI connector system and connection method includes providing a two-channel header having two ground buses, to which the alternating electrical ground wires of respective first and second SCSI channels are terminated. Only a few of the pins or positions of the two-channel connector are connected to the two ground buses while the majority of pins or positions are connected to the signal (control, data) wires of the two SCSI channels.

Abstract: A shared system memory buffers data transfers between a plurality of host computers and a plurality of data storage devices. The system memory includes a cache memory and a number of queues and structures to facilitate performance. Management of a replacement queue within the system memory is based on the elapsed time and usage of the data element. If the elapsed time of a data element to be updated is less than a threshold, the data element will remain in the same location of the replacement queue; if the elapsed time is greater than the threshold, the data element is placed at the tail of the replacement queue. The threshold may be determined by dynamically monitoring the stress of the cache memory. The updating of the replacement queue is also affected by the number of times the data element has been accessed while in the replacement queue. The memory also includes a pending write data structure which is not part of the replacement queue.

Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module. The filter/buffer module filters and buffers the information received from the mass storage subsystem and provides the buffered information to the tape log module for storage.

Abstract: A method of prefetching data from the storage media of a data storage system, in which the data is stored on, and read from, the storage media in individually-accessible data storage portions, such as tracks of a hard disk. A number of immediately past-read data storage portions are used to predict a storage portion or portions that will likely be requested in the future. The unique identifiers of those previously-read data storage portions are determined, and a prediction coefficient is calculated for each unique identifier. The prediction coefficient is then multiplied by the unique identifier, and the results are summed to determine the unique identifier of a data portion to be prefetched.

Abstract: A cache management system and method monitors and controls the contents of cache memory. A time indication provider provides a time indication signal to a cache indexer, for maintaining a cache index which are stored in cache as well as an indication that a data element must be written to a longer term data storage device. A cache manager is responsible for placing data elements into and removing data elements from the cache memory. The cache manager is responsive to at least one data element stored in cache which must be written to a longer term data storage device, and to the associated time indication, for determining the amount of time that the data element has been stored in cache as well as the average period of time that elapses between a data element being inserted in cache and being removed from cache.

Abstract: A computer system for connection in a network, which has a number of other devices each of which may receive communications from the computer system. The computer system includes a network interface and a message transmission control circuit. The network interface establishes a communications session with a selected one of the other devices as a destination for transmitting messages to the selected device. The message transmission control circuit enables the network interface to establish a communications session and transmit messages thereover with the selected device. The message transmission control circuit initially enables the network interface to transmit a number of messages corresponding to a log-in credit value selected for the selected device. Thereafter, the message transmission control circuit enables the network interface to transmit message based on flow control information received from the selected device.

Abstract: A method and apparatus are for maintaining a cyclic redundancy check (CRC) byte is described which eliminates additional input/output (I/O) transactions for the case when a write to a partial sector is required while the CRC byte is maintained for an entire sector. The method includes performing an XOR operation between the partial write data and the data it is to displace, and then performing an XOR operation between the old CRC byte associated with the sector and the result of the XOR operation between the partial write data and the data it is to displace.

Abstract: A storage and retrieval system for a plurality of data storage media includes a 3-dimensional data storage media storage cabinet having a plurality of moveable data storage media storage locations, at least one of which is empty or unused. Each data storage media storage location is moveable along at least two orthogonal axes, to facilitate retrieval of a selected one data storage media. Each data storage media is indexed in a data storage media system controller. When access to a predetermined one data storage media is requested by a command or request from a data processing system such as a host computer, the data storage media system controller, utilizing the index, determines the media transport control signals required to effectuate the quickest access to the media. A retrieval mechanism retrieves the media from a retrieval region in the storage cabinet and places the media into and out of a read/write mechanism, to allow access to the data storage media.

Abstract: A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.

Abstract: A network includes a plurality of computer systems interconnected by a plurality of communication links. At least one of the computer systems includes a resettable computer and a reset circuit. The reset circuit is actuable in response to the receipt of a message containing a received reset code value for generating an interrupt signal and to begin a timing interval, and at the end of said timing interval to generate a reset signal. If the computer is in its normal operational condition, it is responsive to the interrupt signal from the reset circuit to deactuate the reset circuit prior to the end of the time interval to prevent the reset circuit from generating the reset signal. On the other hand, if the computer is in the hung condition, it does not respond to the interrupt signal, and so the reset circuit at the end of the time interval will generate the reset signal to enable the computer to initiate a reset operation.

Abstract: First and second pairs of pins and cooperative first and second pairs of pin receiving apertures are provided at the confronting connector faces of each of one or more data storage device carrier subassemblies and an interconnection board of a storage system card cage subassembly into which each data storage device carrier subassembly is slidably mounted. The first pin/aperture pair engage and cooperate first to prealign, mechanically support and vibrationally damp each data storage device carrier subassembly.

Abstract: A method for adjusting the tension of a tape in a tape drive is disclosed. The tape is loaded into the tape drive. A test signal is then provided to record test information onto the tape while the tape tension is varied concurrently in a prescribed manner. The test information is read immediately to provide a test readback signal. The test readback signal is processed to determine a functional relationship between the test readback signal and the tape tension. An operating tape tension value is computed based upon the functional relationship. The operating tape tension is implemented on the tape drive in the form of a command signal to a motor means of the tape drive.

Abstract: To prevent simultaneous usage of selected data signal groups in a data processing system, techniques are described to restrict such usage. First, with each location capable of storing a data signal group, a register cell can be assigned either in the main memory or in the cache memory units. When a data processing unit requests the data signal group, the register cell associated with each location in which the requested data signal group is stored has a control signal stored therein, and the control signal prohibits usage by another data processing unit. At the end of the activity, the requesting data processing unit removes the register cell control signal from all the locations storing the requested data signal group and the data signal group is then available to any requesting data processing unit.

Abstract: In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.