Abstract: An analog measuring system is disclosed which simultaneously stores in a first memory element a voltage generated by a physical phenomenon including the errors introduced by the measuring system and in a second memory element a voltage corresponding to the errors introduced by the measuring system. Subsequently, the voltages are combined so that true electrical representation of the physical phenomenon is provided. Additional means are disclosed which establish a reference for the physical phenomenon. The electrical representation of the reference is combined with the electrical representation of the sensed physical phenomenon to provide an absolute reading. Thus, the measuring system provides an electrical representation of the physical phenomenon which is independent of time, temperature and frequency.

Abstract: A circuit for filtering electrical waveforms in which the useful information is contained in patterns and spacing of zero-voltage crossings is disclosed. Illustratively, a disk memory system is disclosed in which the voltage peaks developed by the disk memory read-transducers are converted into zero-voltage crossing waveforms by differentiation. To eliminate false zero-voltage crossings caused by noise, the digital filter generates a linear ramp waveform whose magnitude is proportional to the time duration between successive zero-voltage crossings. False zero crossings typically have a short time duration between successive crossings. They are eliminated from the integrated ramp waveform by a comparator which only responds when the integrated waveform reaches a predetermined threshold level indicating the time between successive zero-voltage crossing exceeds a minimum time duration.

Abstract: A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity.

Abstract: A modular electrolytic recorder comprises four mechanical subassemblies and one electrical module for easy construction and replacement. Upon the chassis subassembly is mounted the anode subassembly including a flexible anode, a helix drum subassembly and a gear box transmission subassembly to which is attached the printed circuit board electrical module.

Abstract: A video terminal system having a plurality of distinct output devices providing humanly perceivable, alphanumeric information is disclosed. The video terminal processes and transfers the binary representations of each alphanumeric character to a character generator. A dot matrix corresponding to the character is provided by the character generator and is time-multiplexed so as to be time-shared by each of the output devices without the requirement for specialized circuitry and with minimal time degradation. The distinct output devices may be video displays and hard copy printers which display alphanumeric characters for a complete line, the video display devices receiving each complete line of characters in a predetermined time period and the printer devices receiving a slice of each character for a line upon request.

Abstract: A high speed display processing unit (DPU) for displaying vectors on a cathode ray tube is disclosed. Each vector to be displayed is classified as to whether it is virtual, visible or both. If the displayed vector is partially visible, a digital section of the DPU calculates the length of the visible portion of the vector. Prior to drawing the vector, the digital section determines the major axis of the vector and its tangent. Each of the above values is provided to an analog section of the DPU which then draws at a constant velocity the visible vector. The DPU also includes circuitry for scaling, offset calculations and light pen hits.

Abstract: When two asynchronous signals may occur at approximately the same time, only one of the signals being able to control consequent events, a circuit accounts for the conflict situation by selectively adding a delay until the conflict situation has settled. While the circuit does not determine which asynchronous event may control, the selective delay extends the time for the decision to be made. This circuit provides high reliability while minimizing delays and eliminates the need for indiscriminately adding a delay to each asynchronous event so as to resolve conflict situations. The circuit has particular applicability to volatile memory systems wherein conflict between processor requests and refresh requests to memory occur and allows processor requests to proceed with minimum delay in nearly all situations.

Abstract: In a video terminal system wherein a number of characters are to be displayed on each forward horizontal scan, a scan control circuit is utilized to synchronize the displaying of characters with the scanning of the cathode ray tube. Both the scan control circuit and the displaying characters are tied to a timing chain. Since the displaying of characters occurs at a fixed predetermined time in the timing chain, the scan control circuit is required to control the movement of the scan such that the phase of the scan is regulated in time. The scan control circuit accomplishes synchronization by a self-regulating feedback circuit which controls the magnitude of the base drive to a power transistor. Since the storage time of a power transistor is proportional to the magnitude of the base drive current to the power transistor, a simplified circuit results which accurately places the characters at a fixed position.

Abstract: In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative digital decoding and ensures a precise data transfer to a computer interface. One of the delay circuits enables a data reconditioner circuit to buffer the data and eliminates data peak shifting. The reconditioned data is provided to a coincident circuit which selectively transfers the data to a computer interface and to a phase difference detector. The other delay circuit provides to the phase difference detector a second input corresponding in time to the coded incoming data pulses. The detector's output generates a DC error voltage which synchronizes a voltage controlled oscillator (VCO). The outputs of the VCO are clock pulses in phase with the coded incoming signals.

Abstract: A self-zeroing, drift-free analog-to-digital conversion system is disclosed in which a single amplifier is shared between an analog-to-digital converter circuit and a sample-and-hold circuit. The offset errors generated by the sample-and-hold circuit cancel with the offset errors generated by the analog-to-digital converter circuit since the circuitry introducing the offset errors is shared. As a result, system offset errors are negated and the system enables changing from a unipolar to bipolar input range without inclusion of any additional circuitry. Usage of a gain preamplifier is provided with no corresponding system offset errors being introduced. moreover, usage of a differential-input gain preamplifier is also provided, with the self-zeroing feature resulting in greatly improved common-mode rejection.