Abstract: In a computerized simulation system, the behavior of a model comprising a group of interrelated objects in an object oriented programming environment is defined by a constraint network including temporal constraints, which the future behavior of the model must satisfy following triggering events. Following a triggering event, time stamped representations of messages are created and stored in a queue. The value of a time variable representing time is progressively incremented and the message indicated by each enqueued representation is sent to the model as the value of the time variable surpasses the value of the time stamp of the representation. The message representations and the value of their time stamps are created according to the requirements of the constraint network such that the messages cause the model to perform the appropriate actions at the appropriate times in order to satisfy the temporal constraints defined by the constraint network.

Abstract: A rule acquisition method for expert systems receives input from the expert, one word at a time, and checks each word by determining alternative parses for the partial sentence as so far entered. Feedback is provided to the expert when a word does not conform to a required grammar, this feedback comprising a menu of legal next choices. When the sentence is completed it is translated into the form of a diagnositc rule. An expert system for troubleshooting electronic equipment is disclosed employing rules generated in the aforementioned manner.

Abstract: A multistage digital filter for producing an output data sequence in response to elements of an input data sequence includes a multiplier for multiplying elements of the input data sequence by selected coefficients to produce product terms. An accumulator sums product terms to produce elements of a first filter stage output sequence and elements of the first filter stage output sequence are sequentially fed back to the multiplier. The multiplier and accumulator produce accumulated sums in response to the first stage output sequence to provide a second filter stage output sequence. In a similar fashion, each filter stage output sequence is fed back to the multiplier as the input sequence to the next filter stage until the output sequence of the last filter stage is produced.

Abstract: A digital bandpass oscilloscope permits an operator to observe both time and frequency domain plots of analog signal components of frequency within a passband of selected center frequency during a time window of selected duration. The input signal is digitized, and the resulting digital data sequence is bandpass filtered and decimated by an adjustable decimation ratio to produce stored waveform data indicating the time dependent behavior of the passband during the time window. The oscilloscope, which utilizes the waveform data to produce both time and frequency domain displays of the passband, adjusts the decimation ratio to ensure that the number of data elements in the waveform data sequence is constant regardless of the selected duration of the time window and adjusts the bandwidth of the passband to minimize aliasing in the time domain display.

Abstract: A trigger re-synchronization circuit providing reduced trigger gate jitter for use in a high speed display device such as an oscilloscope or digitizer. The trigger re-synchronization circuit is cascadable.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: A predictive time base control circuit for a waveform sampling system of the type which converts a sequence of analog waveform samples into a sequence of digital quantities for storage in an addressable acquisition memory. The time base circuit generates a sampling control signal which initiates sampling at the end of a time interval of programmable duration following detection of a triggering event in the waveform, and which maintains sampling thereafter at regular intervals. The time base circuit permits the sampling system to operate in an equivalent time mode in which repetitive waveform sections are sampled at progressively skewed sampling intervals with respect to a repetitive triggering event. The sampling control signal is also frequency divided, delayed, and then applied as a write control signal to the sampling system acquisition memory.

Abstract: An adaptive filtering procedure reduces overshoot which may be present on a waveform having infinite slopes displayed on a digital oscilloscope as a result of interpolation between samples at the location of the infinite slopes. An adaptive filtering procedure identifies sampled points adjacent the infinite slope and moves the points closer to each other to avoid ringing or overshoot on the display. Before modification, a straightness test relative to the waveform before and after a discontinuity and a test for sudden changes in the waveform before and after the discontinuity are performed.

Abstract: An adjustable support allows a computer terminal or display device to be conveniently positioned above a desk. The support includes a platform for holding the terminal and a pivotally connected linkage assembly comprising proximal and distal arms for vertically and horizontally positioning the platform, the distal arm having the platform mounted thereon. The proximal arm comprises a set of members forming an articulated parallelogram structure, the proximal end of which is rotatable about a vertical post clamped to the desk. The vertical position of the terminal may be adjusted by changing the shape of the articulated parallelogram structure. As the shape of the parallelogram structure changes, the elevation of the distal end of the proximal arm changes which in turn affects the vertical position of the platform and display device.

Abstract: A variable resolution system for a potentiometer converts the analog output of the potentiometer to digital steps which are multiplied to provide a number of digital output steps dependent upon the extent of potentiometer movement since last reversal. Upon each reversal, the number of output steps per input step is reduced to provide greater resolution.

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

Abstract: An automatic picture coding system including a method for converting a bit-map image of the picture to vectors as the picture is being scanned. The bit map is delayed as it is being generated to form a series of tessellations or windows of data. The windows are propagated through a series of neighborhood-logic elements which perform data transformation operations such as growing, smoothing and thinning of the bit-map image. A bit stream output from the neighborhood logic which output includes only line and edge features of the original picture is transferred serially to a microcomputer where the features are partitioned into a plurality of line segments. Each line segment is chain coded and temporarily stored, as it is acquired, in a corresponding one of a plurality of lists, the lists being linked in an order corresponding with the order in which the segments are acquired.

Abstract: Information for a histogram is provided through generation of a pseudo-random sequence in a shift register connected in predetermined feedback relation. A histogram element storage location is addressed in a random access memory and is used for loading the shift register in parallel when an event corresponding to that element takes place. The shift register proceeds from that point to increment a pseudo-random sequence for the duration of the event, and the concluding value of the sequence is loaded back into the random access memory location at the conclusion of the event. A network between the random access memory and the shift register loads the shift register with a pattern that replicates the pattern that would exist in the shift register if the shift register had already been loaded and the data therein was shifted once.

Abstract: In a multiple trace oscilloscope wherein separate traces displayed on a cathode ray tube screen are updated in succession, a random access memory is addressed by the count output of a programmable counter which increments its count each time the oscilloscope finishes updating one trace prior to updating a next trace. Data stored in the random access memory at the storage location addressed by the count is utilized to control attributes of the next trace to be updated by controlling the switching positions of attribute control switches which select the horizontal, vertical and intensity control signals controlling the appearance of each trace.

Abstract: For a computer system having peripheral devices coupled to a common bus through interface devices transmitting and receiving messages containing an address code matching a stored address code, a dynamic address assignment system stores a unique address code in each interface device following system startup. On system start up each interface device stores a type number and an adjustable serial number, type numbers for peripheral devices of the same type being identical while serial numbers for all peripheral devices of the same type are adjusted to different values. A master controller transmits to all peripheral devices a series of universally addressed count commands. Each interface device counts the count commands and, when the count reaches a poll number determined by the unique combination of stored type and serial numbers, requests and obtains a unique address code from the host computer.

Abstract: A control circuit produces a control voltage for a tunable delay line in response to the magnitude of digital input data. The magnitude of the control voltage output corresponding to any digital input magnitude is independently adjustable to compensate for any nonlinear response of the delay to control voltage input such that the time delay produced by the delay line is substantially a linear function of the digital input to the control voltage source.

Abstract: A voltage controlled, triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: A pulse generator utilizes a pair of current sources acting through a pair of Schottky diode switches to provide load currents in opposite directions through a load resistor to produce an output voltage across the load resistor of magnitude proportional to the difference between the load current magnitudes. The pulse generator output voltage is abruptly driven to zero potential by applying balanced, rapid slewing voltage pulses to the Schottky diode switches, causing the switches to simultaneously divert the load currents from the load resistor. The balanced voltage pulses are developed at the terminals of a step-recovery diode by switching the step-recovery diode from forward to reverse bias state.

Abstract: A data compression circuit has a compression mode of operation where it determines and stores minimum and maximum values of successive sequences of applied data words and provides an output comprising a pair of data words representing the stored minimum and maximum for each sequence, offset by a selected amount. The circuit also has a transparent mode of operation where output data sequences match input data sequences.

Abstract: A transaction analyzer, for use in conjunction with a data acquisition system having a probe for accessing binary data, i.e. address and control signals appearing at the terminals of an operating microprocessor, determines the type of processor transaction occurring based on sequences of state changes occurring on a selected set of the control signals so accessed. The transaction analyzer then generates a binary number representing the transaction type which may be acquired by the acquisition system in conjunction with the data accessed by the probe. The transaction analyzer, which uses an asychronous state machine, also generates control signals used by the acquisition system to clock data storage along with a signal to control the direction of flow of data signals between the processor and the acquisition system.