Abstract: A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset.

Abstract: An angle modulated periodic waveform is synthesized by generating three digital number sequences. In a first number sequence, one number thereof is generated on each occurrence of a periodic clock signal and has a magnitude which is a selected first periodic function of the number of prior occurring clock signals. In a second number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected second function of prior occurring numbers of the first number sequence and an applied constant carrier waveform frequency parameter. Each number of the second number sequence is added as it is generated to a stored second address number. In the third number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected third periodic function of the stored second address number.

Abstract: In an oscilloscope, a readout control circuit is adapted to create a horizontal cursor on an oscilloscope screen at a vertical level controlled by cursor level data generated by a microcomputer, and to cause the beam to form characters on the screen indicating a voltage represented by the vertical level of the cursor. Vertical offset and vertical gain parameters characterizing a vertical preamplifier system controlling display of a waveform are measured and utilized to determine the value of cursor level data needed to cause the readout control circuit to position the cursor on the screen to accurately reflect a selected voltage with respect to voltage magnitudes represented by points on the displayed waveform.

Abstract: A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are identically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appropriately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselected rules during a memory write operation prior to being written into memory.

Abstract: An asychronous state machine waits a variable length of time after first detecting a change in input state before initiating a machine state change, the new machine state being a function of the previous machine state and the input state at the end of the waiting time, thereby allowing multiple, non-simultaneous input changes to occur during said waiting time without initiating intermediate state changes. The waiting time is a function of the current state of the machine. One state variable of a set characterizing the current state of the machine indicates whether the current state is an interim state in a sequence of states occurring after an input state change. Following a machine state change, this sequencing state variable initiates a subsequent state change, in the absence of any further input state changes, when the sequencing state variable associated with the current machine state indicates that the current machine state is such an interim state of a sequence of states.

Abstract: A probe for coupling electrical test equipment to a selected point of an electrical device has a resiliently supported rigid pin for contacting the selected point and a wave guide of substantially constant characteristic impedance coupling the test equipment to the pin.

Abstract: A multiplexer samples multiple analog waveform signals to provide a sequence of input signals to an active low-pass filter. The bandwidth of the filter is determined by an input RC network having series resistance and shunt capacitance elements. As the multiplexer switches state to sample a different analog signal, the resistance elements of the filter are temporarily shorted to allow the filter input signal to rapidly charge or discharge the shunt capacitance element to a steady state voltage in response to any change in input signal voltage. The resistance elements are then unshorted to permit normal low-pass filter operation. Switch means are also provided to selectively disconnect the shunt capacitance element from the network when the resistance elements are shunted, thereby selectively widening the bandwidth of the filter to pass higher frequency input signals.

Abstract: A graphics display terminal performs a pan operation with respect to a view motion center to effectuate spherical panning, thereby providing perspective and non-perspective views. Three dimensional instructions stored in terminal memory are re-transformed in accordance with a panned direction. Also a zoom feature is provided so that displayed images may be magnified as desired.

Abstract: A testing method and apparatus employs electron beam writing and reading of conductive paths in a circuit device rather than physical probing of conductive elements. Portions of the circuit device, e.g., conductive paths, are bistably stored at a given potential and then the device is read by a reading beam to determine if proper connections exist. Read out is at comparatively high levels represented by the difference between bistable voltage values. Once a portion of the device has been tested, it may remain in stored condition such that additional cross checking or repetition of testing is rendered unnecessary.

Abstract: An encoder circuit converts a thermometer code into an equivalent adjacent binary code wherein only a single bit is changed to minimally increment or decrement the value of the binary code. The encoder logic is grouped so that the state of any single bit of the thermometer code can affect the state of one and only one bit of the binary code whereby when any least significant thermometer code bit is at an invalid logic level, the invalid level is propagated through the encoder circuit to only a single, least significant binary code bit, without the introduction of any logical errors. The invalid binary code bit is then stabilized to a valid level by one or more latches.

Abstract: Color dither patterns are read into a pixel bit map memory used to form a color display by means of concurrently addressing a pattern memory storing the dither patterns. Lower order address bits repeatedly access a preselected portion of the pattern memory to supply the dither pattern which is written as data into the pixel bit map memory.

Abstract: A timebase generator includes a transistor switch performing a sweep gate function, alternately providing a current path for retrace and then disconnecting such current path to allow generation of a time base ramp. The bias current delivered to the switch is controlled to be at a high level for bringing about proper retrace, but at a low level at the beginning and ending of the time base sweep itself to prevent undesired transients and nonlinearity effects. The low current is maintained from the end of the retrace period until the start of the following retrace period. A baseline stabilizer loop comprises a transistor circuit for accurately predetermining the baseline reference wherein the emitter current of the transistor is controlled to a substantially constant value during operation for enhanced stability.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

Abstract: A keyboard encoding circuit includes a first and a second set of resistors and a switching matrix divided into a plurality of switch banks, one switch bank corresponding to each resistor in the first set. Each switch bank comprises a plurality of switches with each such switch in a bank corresponding to a resistor of the second set. Each resistor in the first set has one terminal coupled in common to a supply lead of a source of DC current and a second terminal coupled to a first side of each switch in the corresponding bank of switches. Each resistor in the second resistor set has one terminal coupled to a second side of corresponding switches in one or more switch banks and a second terminal coupled to a return lead of the DC current source.

Abstract: A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.

Abstract: In a graphics display system, a cursor is used to pan a viewport relative to a block of stored information only part of which is selectable to be viewed through the viewport. As long as a cursor remains within the viewport, it can be utilized in a conventional manner under the control of a mouse or the like to provide interaction with display information. When the cursor is moved outside the viewport of the display, the viewport is panned to include the cursor.

Abstract: A method for providing test vectors adapted to test very large scale integrated circuit devices includes the steps of measuring testability employing a test counting procedure to provide a plurality of test count matrices. Sensitivity values are then enumerated by driving individual sensitivity values forwardly and rearwardly through the circuit, starting at the input terminals, until the test counts are accumulated. The enumerations define test vectors capable of testing the actual circuit. If the circuit includes reconvergent fanout loops, then these loops are enumerated first to provide partial solutions adopted during subsequent global enumeration.

Abstract: An apparatus for performing ratiometric capacitance measurements by comparing the output of a digital-to-analog converter with the voltage at a tap between an unknown capacitance and a first inherent capacitance of the apparatus. A common input voltage is supplied to both the series circuit, including the first inherent and unknown capacitances, and to the digital-to-analog converter which accomplishes attenuation of the input voltage in response to a digital value. The digital value is generated by a successive approximation register supplying a digital output relating the unknown capacitance to the known capacitance. The apparatus is adapted to ratiometrically measure the first inherent capacitance by supplying the common input voltage to a series circuit, including a known reference capacitance and the first inherent capacitance, such that the digital output of the successive approximation register relates the first inherent capacitance to the reference capacitance.

Abstract: In a system for generating a vector representation of a waveform on a cathode ray tube screen, the minimum and maximum magnitudes of an analog waveform acquired during each of successive measurement periods are stored in a random access memory, with the minimum and maximum signal values for each measurement period being stored in arbitrary order. The minimum and maximum signal values within each measurement period are then time sequenced by selectively comparing the minimum and maximum values obtained during each such measurement period with the values obtained during preceding and/or succeeding periods. Also according to these selected maximum and minimum comparisons, the maximums obtained during selected measurement periods are decremented by a selected amount while minimums obtained during selected periods are incremented by a selected amount.

Abstract: A high performance color cathode ray tube is manufactured by welding a shadow mask under very high tension to a metal ring brazed to the tube envelope. The shadow mask material has a high yield strength and a thermal coefficient of expansion near that of the ceramic ring portion of the envelope to which it is secured.