Patents Represented by Attorney, Agent or Law Firm John R. Ley
  • Patent number: 6557566
    Abstract: A drum washer has a base, a barrel support structure, and a water delivery system. A hollow drum is turned over and placed on the drum washer by inserting a spray head of the water delivery system through a hole in a top cover of the drum and into the interior of the drum. The barrel support structure holds the drum at a fixed angle while water is sprayed from the spray head onto interior surfaces of the drum. The water rinses the interior surfaces of the drum and drains out the hole in the top cover of the drum.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: May 6, 2003
    Assignee: LSI Logic Corporation
    Inventor: Don Rudolfs
  • Patent number: 6553511
    Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: April 22, 2003
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Thomas L. Langford, II, Scott E. Greenfield
  • Patent number: 6530511
    Abstract: Wire from a wire source is supplied to create a predetermined amount of slack wire in a predetermined configuration and to maintain that slack wire configuration. Some of the slack wire is withdrawn from the configuration and advanced for use in forming an electrical connector. As wire is withdrawn from the slack wire configuration, additional wire is supplied to renew and maintain that configuration. A characteristic of the slack wire configuration is sensed to control the amount wire supplied. In this manner, the mass and rotational effects of unwinding wire from a spool while simultaneously advancing that wire are avoided, thereby avoiding wire slippage and allowing the constituent components of the connector, such as bulges of a twist pin connector, to be more precisely located during fabrication.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: March 11, 2003
    Assignee: Medallion Technology, LLC
    Inventors: Steven E. Garcia, Randall J. Boudreaux
  • Patent number: 6528759
    Abstract: A segment of wire from which an electrical connector has been fabricated is conveyed from a point where the electrical connector wire segment is severed from a length of remaining wire into a receptacle within which the electrical connector wire segment is stored until use. A reduced pressure is applied by a venturi assembly to the wire segment, and a gas flow conveys the wire segment to the receptacle. A cassette defines the receptacles, and the cassette is repeatedly positioned to each newly fabricated wire segment in a different receptacle.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: March 4, 2003
    Assignee: Medallion Technology, LLC
    Inventors: Steven E. Garcia, James A. Harden, Jr., David A. Hofmann
  • Patent number: 6521549
    Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: February 18, 2003
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Rajiv Patel, Ravindra M. Kapre
  • Patent number: 6511479
    Abstract: A stainless steel electrosurgical blade has a single uniform layer of release material comprising substantially silicone (polysiloxane) applied directly onto the stainless steel blade portion without the necessity of one or more coatings of primer material(s), or multiple layering of the release material or mechanical roughening of the metallic blade body. Adherence of the release coating is achieved by thermally oxidizing the blade body, after cleaning it. The uniform layer is created by dipping the blade body. The release material is preferably thermally cured and non-blooming.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: January 28, 2003
    Assignee: ConMed Corporation
    Inventors: John S. Gentelia, Ronald P. Karpowich, William P. Zobrist, Angel R. Rodriguez, Alexander F. Robb
  • Patent number: 6504202
    Abstract: A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Kenneth Fuchs
  • Patent number: 6498890
    Abstract: The subject matter described herein involves a connector cable, particularly for use in a computerized storage system, such as Fibre Channel. The connector cable generally connects together a storage device, a power supply and an optical cable through which optical signals are transferred. A media interface adapter connects between the connector cable and the optical cable and receives electrical power from the power supply through the connector cable to convert the optical signals to electrical signals and vice versa. Using a plurality of the connector cables with or without a connection to the power supply, a plurality of the storage devices may be chained together.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: December 24, 2002
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Kimminau
  • Patent number: 6480970
    Abstract: Data consistency is verified between geographically separated and connected active and mirroring data processing systems by creating metadata which describes user data, such as a cyclical redundancy code (CRC), and time stamp information which describes the time at which user data was first stored on the active system. The metadata and the time stamp information sent from the active system is compared at the mirroring system with the time stamp information and metadata read from the mirroring system. Upon detecting a discrepancy when comparing the metadata from the active and mirroring systems, the user data from the active or mirroring system which is less current temporally, as determined by the time stamp information, is replaced by the user data from the other one of the active or mirroring systems having the more current temporal time stamp information.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: November 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Thomas L. Langford, II
  • Patent number: 6480643
    Abstract: An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: November 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Verne C. Hornbeck
  • Patent number: 6471716
    Abstract: A photo-therapy device emits photo-therapeutic radiation to treat. living tissue. The device incorporates an array of emitters, the photo emissions of which is dependent on their temperature. Temperature feedback is provided to a voltage supply that supplies current to the emitters, to regulate the voltage supply level and the temperature of the emitters. Additionally, the wavelength of the radiation is dependent on the temperature of the emitters, so the wavelength is moved closer to an optimum wavelength for absorption by the tissue by controlling the temperature of the emitters. Furthermore, the useful life of the emitters is extended by pulsing the emitters on and off by sequentially applying an activation signal to one group of emitters at a time. Also, the device can operate on a wide range of voltage input levels since it utilizes a switching regulator, which can convert a voltage level in the range to the level required to drive the array of emitters.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: October 29, 2002
    Inventor: Joseph P. Pecukonis
  • Patent number: 6466448
    Abstract: Riser printed circuit boards are retained relative to a motherboard to avoid lateral side-to-side movement and vertical separation from an edge connector on the motherboard. A horizontal portion of a retaining plate extends above an upper edge of the riser boards, and a resilient compressible gasket is connected to the horizontal portion. The resilient compressible gasket contacts and upper edge of the riser boards, and applies resilient force to retain the riser boards. The retaining plate also ducts cooling air over heat-sensitive components of the motherboard and increases the air flow rate over those components by reducing the cross-sectional size of the path through which the cooling air flows.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: October 15, 2002
    Assignee: Network Appliance, Inc.
    Inventor: David Baik
  • Patent number: 6461972
    Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: October 8, 2002
    Assignee: LSI Logic Corporation
    Inventor: Alex Kabansky
  • Patent number: 6458508
    Abstract: Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 1, 2002
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Shumay X. Dou, Colin Yates
  • Patent number: 6442741
    Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: August 27, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6441419
    Abstract: An integrated circuit includes a vertical-interdigitated capacitor located between an upper interconnect layer and a lower interconnect layer. Both interconnect layers include conductors formed of a metal capable of atom diffusion or ion migration, such as copper. The capacitor plates contact an interconnect layer conductor to create barrier layers to prevent atom diffusion or ion migration from the conductors at the contact locations. Additional barrier layers contact the conductors at locations other than where the capacitor plate portions contact the conductors, and the additional barrier layers are preferably formed of the same material and at the same time that one of the plates is formed. The integrated circuit may include a via plug interconnect extending between conductors of upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion or ion migration from the plug material.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: August 27, 2002
    Assignee: LSI Logic Corporation
    Inventors: Gregory A. Johnson, Kunal Taravade, Gayle Miller
  • Patent number: 6388486
    Abstract: The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: May 14, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6380776
    Abstract: Digital circuitry synchronizes clock signals in a digital circuit. A value of a reference clock is sampled at a plurality of points near a transition point of a generated clock. It is determined whether the reference clock transitioned from a first state to a second state before, after or within an acceptable range of a transition point of the generated clock. Upon determining that the reference clock transitioned before the transition point of the generated clock, one period of the generated clock is shortened. Upon determining that the reference clock transitioned after the transition point of the generated clock, one period of the generated clock is lengthened.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: April 30, 2002
    Assignee: LSI Logic Corporation
    Inventor: Robert L. Yocom
  • Patent number: 6355532
    Abstract: A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: March 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: John J. Seliskar, Verne Hornback, David Daniel
  • Patent number: 6352355
    Abstract: A decorative, internally-lighted ribbon is formed by a light string and two elongated strips of flexible, semi-translucent material which are connected to form a hollow, elongated sleeve-like enclosure within which a light string is positioned to extend substantially along the length of the enclosure. The semi-translucent material of the strips transfers light from the light string through the strips to create an exterior visual appearance of internal lighting along the length of the ribbon. An internal structure, such as a wire, holds the strips in a flat ribbon-like configuration and allows the ribbon to be bent into decorative shapes. The strips are preferably fire-retardant.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: March 5, 2002
    Assignee: Holiday Creations
    Inventor: Jeremy Law