Patents Represented by Attorney, Agent or Law Firm John R. Ley
  • Patent number: 6656805
    Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: December 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Rajiv Patel, Ravindra M. Kapre
  • Patent number: 6653726
    Abstract: The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: November 25, 2003
    Assignee: LSI Logic Corporation
    Inventors: Richard T. Schultz, Roger D. Weir
  • Patent number: 6651165
    Abstract: A computer system operating system (OS) is booted from a storage media formed from a redundant array of independent disks (RAID). An interface adapter is connected to a system bus, and the interface adapter includes a nonvolatile option ROM memory which has RAID I/O algorithmic instructions recorded therein. When a basic input output system (BIOS) is executed during booting, a BIOS hardware detect instruction set of the BIOS scans the system bus and causes the RAID I/O algorithmic instructions to be read from the option ROM memory for use by a BIOS I/O instruction set, and the BIOS I/O instruction set uses the RAID I/O algorithmic instructions obtained from the option ROM memory to read the OS from the RAID storage media.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 18, 2003
    Assignee: LSI Logic Corporation
    Inventor: Harold L. Johnson
  • Patent number: 6641698
    Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 4, 2003
    Assignee: LSI Logic Corporation
    Inventor: Alex Kabansky
  • Patent number: 6629203
    Abstract: An improved shadow directory technique allocates storage space for directories in pairs in a logical volume. One of the spaces in each pair is used for a directory for locating data in the logical volume. The other space is reserved for an updated copy (shadow) of the directory if the directory is ever to be changed or updated. After the shadow directory is stored, it becomes a new directory for locating the data in place of the previous directory. The storage space containing the previous directory is unused, but retained as allocated for the next shadow directory, if needed. Since directory storage spaces are not deallocated, the improved shadow directory technique enables a simplified sequential-allocation storage management in a primarily data-add environment.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Donald R. Humlicek
  • Patent number: 6626876
    Abstract: A device for the drainage of the bladder through the body's own urethra opening outside of the human body, comprising a tube-shaped body (10). The tube-shaped body is comprised: to assume a first contracted position and for taken up within the bladder as well as a to assume a second partially extended position. At least one thread (14) extends between the bladder and an opening of the urethra and is attached at a first end of the tube-shaped body so that the tube-shaped body can be extended from the first position to the second position during the application of a pulling force upon the thread. The tube-shaped body in the second partially extended position extends in such a manner so as to exceed the distance between the bladder and the point of the urethra's closing. The tube-shaped body is comprised in such a manner that it will return to the first position upon the release of the pulling force on the thread.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: September 30, 2003
    Assignee: ProstaLund Operations AB
    Inventors: Magnus Bolmsjö, Sonny Schelin
  • Patent number: 6614283
    Abstract: In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: September 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Peter Joseph Wright, Venkatesh P. Gopinath, Todd A. Randazzo
  • Patent number: 6605951
    Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 12, 2003
    Assignee: LSI Logic Corporation
    Inventor: Joseph W. Cowan
  • Patent number: 6594744
    Abstract: In a storage system, such as a storage area network, a snapshot volume or one or more checkpoint volumes are formed from the same base volume using a single repository containing multiple images of data stored in the base volume. The first image is started with the formation of the snapshot volume or the first checkpoint volume and is filled with blocks of data copied from the base volume, thereby increasing in size within the repository, until the first image is stopped and the next image is started. The next image is then filled with blocks of data copied from the base volume until stopped. Thus, the blocks of data are copied only into the most recently created image within the repository. With the creation of each checkpoint volume, a new image is concurrently started in the same repository. Each checkpoint volume is dependent on the image that was created concurrently plus any images created thereafter.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 15, 2003
    Assignee: LSI Logic Corporation
    Inventors: Donald R. Humlicek, Rodney A. DeKoning, William P. Delaney
  • Patent number: 6586814
    Abstract: A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Rajiv Patel, David Chan, Arvind Kamath, Ken Rafftesaeth, Venkatesh P. Gopinath
  • Patent number: 6586968
    Abstract: An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bit (LSB) or from LSB to MSB. Therefore, when the first device is used with a second device, integrated circuit (IC) or logic, which can handle the serial data in only one order, the first device is programmed, or configured, to handle the serial data in the same order as the second device.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Steven A. Schauer, David L. Schell
  • Patent number: 6584677
    Abstract: Twist pins having bulges are fabricated from helically coiled stranded wire. Wire is advanced from a source such as a spool to create slack wire configuration, and wire is then advanced from the slack wire configuration to a position where each bulge is formed. Each bulge is formed by gripping the wire in two spaced apart locations and rotating the wire in an anti-helical direction in a single continuous relative revolution to untwist the strands and form the bulge. The wire is thereafter advanced to the position of the next bulge or the position where the wire will be severed to release the fabricated twist pin. The severed fabricated twist pin is conveyed through a flow of gas in a delivery tube into a receptacle of a cassette where the twist pin is stored until used. The cassette is automatically moved to position an occupied receptacle to receive each newly fabricated twist pin.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: July 1, 2003
    Assignee: Medallion Technology, LLC
    Inventors: Steven E. Garcia, Randall J. Boudreaux, James A. Harden, Jr., David A. Hofmann
  • Patent number: 6584361
    Abstract: A device for heat treatment of prostate, comprising a treatment catheter with a fluid reservoir and heating means which is arranged within the treatment catheter and emits electromagnetic radiation for heating of the surrounding bodily tissue. The fluid reservoir constitutes an integrated part of the catheter for treatment and is positioned in the catheter so that, when inserted in a patient, it extends to cover the area heated by the heating means between the prostatic apex and bladder neck. The fluid reservoir also constitutes a closed chamber which is connectable via a channel passing through the catheter for treatment. A stop for the heat-absorbing means is embodied distal to said heating means and distal to said heat reservoir.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: June 24, 2003
    Assignee: ProstaLund Operations AB
    Inventor: Magnus Bolmsjö
  • Patent number: 6575467
    Abstract: Each round of a poker game is played in stages using a conventional deck of cards. A wager is placed at each stage, a hand of cards is dealt to each player at each stage, and the cards dealt to each player in previous stages become part of each players hand of cards at each subsequent stage. A different wildcard is designated at each stage. A winning hand of cards is determined and rewarded at each stage by comparing each players hand of cards including any wildcards to a schedule of winning card combinations and an odds schedule at each stage. At least some of the winning card combinations and some of the odds for each winning card combination are changed at each stage.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: June 10, 2003
    Inventor: Stephen F. Kal
  • Patent number: 6576404
    Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: June 10, 2003
    Assignee: LSI Logic Corporation
    Inventors: John Hu, Ana Ley, Philippe Schoenborn
  • Patent number: 6566730
    Abstract: A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: May 20, 2003
    Assignee: LSI Logic Corporation
    Inventors: Gary K. Giust, Ruggero Castagnetti, Yauh-Ching Liu, Shiva Ramesh
  • Patent number: D477082
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: July 8, 2003
    Assignee: ConMed Corporation
    Inventor: Robert L. Bromley
  • Patent number: D477083
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: July 8, 2003
    Assignee: ConMed Corporation
    Inventor: Robert L. Bromley
  • Patent number: D477408
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: July 15, 2003
    Assignee: ConMed Corporation
    Inventor: Robert L. Bromley
  • Patent number: RE38299
    Abstract: A device for heat treatment of body tissue, including heating means (10) for local heating of the body tissue, and temperature sensing means (11) for sensing the tissue temperature, said heating means being enclosed in a catheter (12). A first temperature sensing means (11) is connected to a first carrier (13), which is made to be advanced through a first opening in catheter (12), and said first carrier (13) is equipped with a pointed tip for insertion into such body tissue that is to be heat-treated.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: November 11, 2003
    Assignee: ProstaLund Operations AB
    Inventor: Magnus Bolmsjö