Abstract: A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator and holding logic. A rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register and causes the pulse accumulator to be incremented. The output of the interval timer can cause the contents of the pulse accumulator and capture register to be stored into the holding logic. The timer apparatus is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

Abstract: A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to provide a plurality of partial products. An additional partial product typically generated during a first iteration of the multiplication operation is provided to a multiplexor (44) and a remaining portion of partial products are provided to a summation tree (40) having a symmetrical circuit layout. [Multiplexor (44) stores the additional partial product until summation tree (40) has processed the remaining partial products to provide a first sum.] When summation tree (40) has processed the remaining partial products to provide a first sum, multiplexor (44) provides the additional partial product to a carry save adder (42). The first sum is added to the additional partial product in [a carry-save] adder (42) to provide a first portion of a product.

Abstract: In a microcomputer including a CPU and a plurality of modules operatively connected through a main bus including address and data lines, a method of interrupting an operation including providing an interrupt request line and an arbitration bus, and arbitrating between modules and with the CPU on the arbitration bus so that no use of the main bus for arbitration or an interrupt acknowledge are required and the CPU can continue the operation as the arbitration proceeds.

Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.

Abstract: A microcomputer interface arrangement includes a microcomputer having I/O ports coupled to individual interface units. A fault detection circuit detects a fault in an interface unit, interrupts the microcomputer and inverts the input state of the faulty unit without affecting the output states so that the faulty unit can be identified by the microcomputer by reading inputs of the interface units.

Abstract: A data processor executes a table look-up and interpolate instruction which retrieves two adjacent table values from memory, interpolates between them and stores the result in a register. The same register contains, prior to the execution of the instruction, a value which is used both in calculating the address in memory from which the values are obtained and in performing the interpolation calculation. A major variant of the instruction involves obtaining the values to be interpolated between from registers, rather than from a table in memory. The combination of the two facilitates the performance of three-dimensional, or surface interpolations. It is also possible to select whether rounding is performed during the interpolation.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers.

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: A microcomputer with an external bus interface for providing communication with external peripheral devices such as memory and the like is provided with on-board chip select logic and programmable bus stretching capability. The chip select logic provides chip select signals to external devices when addresses fall within pre-selected ranges, eliminating the "glue" logic normally required for this purpose. The programmable bus stretching feature inserts a pre-selected number of "wait states" into any external bus cycle for which it is programmed by stretching, or freezing, the central processing unit and external bus interface unit clocks. Other internal clocks, such as those which drive timers and/or serial interface baud rate generators are not frozen by the bus stretch.

Abstract: In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.

Abstract: A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.

Abstract: A data processor in which return from subroutine execution is not dependent on the presence of a particular instruction at the end of the sequence of instructions comprising the subroutine. The disclosed embodiment comprises a micro-programmable processor designed for servicing a timer subsystem. The return from subroutine apparatus comprises a decrementor which may be enabled to decrement once for each instruction executed by the processor and a return address register. A jump to subroutine instruction loads a return address into the return address register, enables the decrementor and loads the program counter with the address of the first instruction of the subroutine. When the decremento reaches a count of zero, the return address is loaded into the program counter. Provision is also made for using the same hardward to execute a single instruction a predetermined number of times before proceeding to the next instruction.

Abstract: A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.

Abstract: A analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), and A/D converter (18), an oscillator (12) and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.

Abstract: A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.

Abstract: An interrupt priority circuit is used with a data processor which is responsive to interrupt signals from each of a plurality of resources of predetermined priority. A priority encoder receives all of the interrupt signals, and provides an interrupt vector corresponding to the interrupt signal received from the resource having the highest predetermined priority. However, the interrupt priority of a selected resource may be dynamically altered to the highest priority by storing a corresponding priority vector into a priority register. A first multiplexor controlled by the priority vector provides an enable signal whenever an interrupt signal is received from the selected resource. A second multiplexor controlled by the enable signal provides the priority vector if the enable signal is present or the interrupt vector otherwise. A gate controlled by the data processor may be provided to selectively couple the vector provided by the second multiplexor onto the address bus.

Abstract: An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or memory table. The command word or words may specify the conversion time per analog input channel or group of channels, and per conversion or conversion sequence. In one embodiment a control table comprises a plurality of conversion command words (CCW's). Each CCW designates conversion parameters including the input sample time.

Abstract: A timer subsystem which provides a data processor servicing the timer subsystem with the ability to inhibit the match recognition logic of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem with a dedicated service processor. The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register, for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.

Abstract: A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.