Abstract: Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

Abstract: A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

Abstract: A data processor (2) including a watchdog timer (8) comprising: a first memory (4) holding a primary operating routine for cyclic execution during operation of the data processor, an address bus (6) for addressing locations in said first memory means, a timer (10) for continuous operation during operation of the data processor and for effecting a system reset in response to the timer reaching a predetermined value, the primary operating routine including at at least one predetermined location an instruction to reset the timer, whereby in normal operation of the data processor the timer does not reach the predetermined value, wherein the data processor further includes a second memory (12) for holding the address of the location containing the instruction to reset the timer, and a comparator (16) coupled to the address bus and the timer for preventing the timer from being reset in response to an instruction to reset the timer unless the address on the address bus is held in the second memory.

Abstract: A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

Abstract: An arithmetic logic unit capable of performing AND, OR, exclusive-OR, and add functions is implemented utilizing strobed gates. An input section receives first and second inputs, each capable of assuming first and second states, and generates a first output indicating that at least one of the inputs is in a first state and a second output indicating that both inputs are in the first state. First, second and third strings of field-effect-transistors controlled by a plurality of control signals are selectively enabled respectively when at least one of the inputs is in the first state, all of the inputs are in the first state, or when only one of the inputs is in the first state. The circuit includes an output section and a circuit for generating a carry-out signal when the inputs so require.

Abstract: Improved logarithmic data compression is achieved by means of a method of finding a more efficient base and a more efficient memory structure. Data compression from a P-bit input word to a Q-bit output word is performed using an optimal base which produces a number of rounded logarithm values equal to 2.sup.Q when applied to all of the possible input values. These logarithm values are coded using the available output values to produce a logarithm look-up table. The look-up table is implemented using a multi-stage memory structure which reduces the number of memory devices required for a given table.

Abstract: An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.

Abstract: A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

Abstract: Improved access to programmable logic arrays is provided by continuously asserting and negating a latch inputs control signal, continuously asserting and negating a control signal which discharges a first logic section of the array to provide frequent, current inputs to a second logic section of the PLA and discharging the second section of the PLA only upon receipt of an access request. In the case of asynchronous access, it is also necessary to generate a synchronized data strobe from the unsynchronized one and to generate an acknowledge signal to indicate the presence of valid output data. The disclosed method and apparatus provide access which has a short access time and which also provides outputs which reflect relatively current states of the inputs thereto.

Abstract: Passivated and low scatter acoustic wave devices comprise surface acoustic wave (SAW) and shallow bulk acoustic wave (SBAW) devices having transducers composed of oxidizable metal and layers of metal oxide on conventional acoustic wave substrates. Passivated transducers are achieved by forming a layer of oxide on an existing transducer. The method may be used to passivate a device packaged in a non-oxidizable package with oxidizable wire leads, thus combining complete protection with efficient manufacturing operations. Low scatter SAW transducers are achieved by forming the transducer and the interstitial insulating layer from a single layer of oxidizable metal by means of masking and oxidation operations.

Abstract: A method for etching multi-layer structures particularly suited for patterning refractory metal silicide/polysilicon sandwiches. A first dry etch process is carried out in a first dry etch chamber and is selected to rapidly and anisotropically etch the uppermost layer, typically a refractory metal silicide. A second dry etch process is carried out in a second etch chamber and is selected to rapidly and anisotropically etch the underlying layer, typically polysilicon, while having a high selectivity to any material underlying the underlying layer. The first process is preferably a fluorine-chemistry process with low frequency RF energy and the substrate resting on the grounded electrode. The second process is preferrably a chlorine-chemistry process with high frequency RF energy and the substrate resting on the powered electrode.

Abstract: A semiconductor device ejector/sorter for use in an automated handler for randomly sorting a sequential input of semiconductor devices to one of a series of output tracks depending on a predetermined condition. As each semiconductor device is moved into alignment with the appropriate output track, a controller operates an ejector which uses a flexible push rod to eject the semiconductor device onto the track.

Abstract: An integrated circuit sleeve handler comprises an input hopper, a first conveyor for sequentially removing individual sleeves from the hopper, an orientor for uniformly orienting the sleeves, a second conveyor for cooperating with the first conveyor to align each sleeve at a sleeve unloading station, a buffer for temporarily holding empty sleeves, a third conveyor for receiving empty sleeves from the buffer and moving them to and past a sleeve loading station and to an output bin and a fourth conveyor for cooperating with the third conveyor to align each sleeve with the sleeve loading station. Thus, all of the sleeve handling needs for an automated integrated circuit handler can be met with a single apparatus which needs very little manual intervention.

Abstract: An end cap for an integrated circuit sleeve comprises a body portion which fits inside the sleeve and prevents unwanted removal of integrated circuits therefrom and a passage through the body portion which is adapted to permit passage of a pusher mechanism therethrough. The pusher is inserted into the sleeve through the end cap to push integrated circuits out of the opposite end of the sleeve. This end cap reduces the amount of pre- and post-handling manual labor involved in insertion and removal of end caps by one-half.

Abstract: A circuit for selectively determining whether a first number is greater than or equal to or less than or equal to a second number, comprising a means for adding a first number and a complementary function of a second number, and logic means for generating a signal for carry-in and for combination with a carry-out of the means for adding for producing a signal indicative of whether the second number is within the parameters established by the first number and the carry-in.

Abstract: A multi-wafer load lock apparatus for use in wafer processing machines provides access to wafers in an internal cassette by orthogonal wafer transport devices. Upper and lower bell jars, which seal to a sealing plate, provide access to the cassette by outside and vacuum transport mechanisms, respectively. A right angle passthrough cassette allows orthogonal access. An improved vacuum feedthrough actuates both the upper bell jar and the internal cassette.

Abstract: Passivation, alpha protection and other relatively thick, patterned layers are applied to semiconductor wafers by a screen printing method. Patterned emulsions carried on fine mesh stainless steel screens are tempered at elevated temperatures to harden the emulsion. The screens so prepared withstand many cycles of printing and cleaning with harsh solvents present in screenable polymers such as polyimide and rigid silicone.

Abstract: Packaging of discrete semiconductor devices is improved by dimpling metal caps prior to assembly onto headers and welding.The dimpled caps provide a friction fit to the headers, whereby fewer assembled, but unwelded packages separate during handling. The dimples are more economical and more reliable than prior art crimps which perform a similar function.

Abstract: Wafer transport in the vacuum portion of an automated wafer processing machine is accomplished by means of an improved transport mechanism. The primary transport device is a rail guided, magnetically driven shuttle plate. Baffles serve to isolate the particle producing portions of the mechanism from the wafers. The major drive components are located inside the rails and outside the vacuum containment system. A pin lift apparatus located on the reactor chucks serves to remove and replace wafers on the shuttle plate. The disclosed apparatus provides efficient and reliable wafer transport with a minimum amount of particulate generation and is easily reconfigurable to single or multiple head machines.

Abstract: A process monitor which is particularly useful for endpoint detection in plasma etching processes does not require the dedication of a test area on the wafer for endpoint detection and also obviates the need for wafer alignment. An improved optical window which does not significantly perturb the RF fields in the plasma chamber is also disclosed. The apparatus reflects laser energy off an area of the wafer comparable to the area of a typical die and extracts the necessary information from the resulting waveform by means of first and second time derivatives.