Abstract: An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.

Abstract: A digital data processor of the type having a plurality of data inputs and a plurality of data latches, each coupled to one of said data inputs is modified to accomodate pattern driven interrupt. A plurality of bit comparators, each having inputs coupled to one of the said data inputs and one of said data latches, compare the input pattern to a stored pattern. The outputs of the bit comparators are ANDed to indicate one of a match and a mis-match between the two patterns. Interrupt generation logic is selectable to generate an interrupt request on one of the match and mis-match indications. The apparatus and method are particularly suited to use in a microcontroller which requires fast and software-efficient pattern driven interrupt.

Abstract: A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Abstract: A timer system comprises a plurality of timer channels serviced by a single service processor. Each of the timer channels is capable of both input (capture) and output (match) functions. The microprogrammed service processor is responsible for configuring each of the channels for their intended uses and for responding to service requests generated by the channels in response to the occurrence of timer events. Features of the timer channels include the ability to continuously execute capture functions without generating service requests, the ability to execute a single capture function and service request and protect the captured value from being overwritten until the service request has been responded to and the ability to combine match and capture functions in such a way as to place a time-out window on the capture event.

Abstract: A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.

Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.

Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.

Abstract: An overload circuit detects input signals that are too high or too low in amplitude and generates a holding signal of a predetermined duration. The holding signal is applied to a data selector which normally passes the input signal to a shift register/majority gate but switches to supply the output of the majority gate to the shift register when a holding signal is present. Thus, the output is maintained constant during the predetermined durations when a holding singnal is present.

Abstract: A method and apparatus for post-packaging testing of one-time programmable memories provided means for assuring that each cell of the memory will appear to a customer to be erased and that it is capable of being programmed. The preferred embodiment of the invention is a microcomputer including one-time programmable memory, but the invention also includes memory-only devices. Marginal reading method and apparatus provide for detecting the threshold voltage of memory cells below the level at which the cell appears to the customer to be erased and marginal programming method and apparatus provide for slightly increasing the threshold voltage of cells in order to ensure their programmability.

Abstract: A method of data reduction in non-coherent SLAR systems enhances the usefulness of such systems in moving target environments. Digitized MT data is processed to identify and classify target footprints. At least some of the footprints are replaced by an indicator of the centroid thereof and its motion. Clutter is rejected. Other footprints are replaced with truncated versions thereof. The technique is suitable for real time application.

Abstract: An improved monolithic, temperature compensated voltage-reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The junction between the tub and the substrate forms the forward-biased, temperature compensating junction of the device. The dopant concentration is varied during growth of the epitaxial material to provide a relatively low resistivity at the voltage-reference junction and a higher resistivity at the temperature compensating junction. The method described offers significant improvement over prior methods of manufacturing such devices in the area of cost and reliability.

Abstract: A barrel shifter comprises a first plurality of bit lines, a second plurality of bit lines and a plurality of switchable interconnections therebetween. A first subset of the switchable interconnections provide each of a set of desired shifts, while a second subset of the switchable interconnections duplicate certain of the first subset thereof and shorten the worst-case path lengths through the shifter. The first and second pluralities of bit lines may comprise interleaved high- and low-order bit lines of two data buses. Interface means may provide the interleaving function and also may provide means for accomplishing at least one shift in addition to the set of desired shifts. Sense amplifiers may be included for sensing voltage transitions on each bit line.

Abstract: A serial peripheral interface achieves compatibility with devices having previous such interfaces while significantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Abstract: A method and apparatus for post-packaging testing of one-time programmable memories provides means for assuring that each cell of the memory will appear to a customer to be erased and that it is capable of being programmed. The preferred embodiment of the invention is a microcomputer including one-time programmable memory, but the invention also includes memory-only devices. Marginal reading method and apparatus provide for detecting the threshold voltage of memory cells below the level at which the cell appears to the customer to be erased and marginal programming method and apparatus provide for slightly increasing the threshold voltage of cells in order to ensure their programmability.

Abstract: A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.

Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.

Abstract: Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in first predetermined states; a set flag operation places both elements in second predetermined states; a read flag operation alters the state of the second storage element; and a clear flag alters the state of the first storage element if and only if the state of the second storage element has previously been altered by a read flag operation. The flag output corresponds to the state of the first storage element. When implemented with single instructions, inadvertant flag negation and errors due to intervening interrupts are avoided. The read flag operation temporarily disables the set flag mechanism, protecting against setting the flag during a read operation. The flag is always read as asserted prior to being negated.

Abstract: A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.

Abstract: A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot be written into the protect register except during a short, predetermined period after the occurrence of an event such as a reset. The protect register may be written to with information other than the predetermined information at any time. The preferred embodiment comprises a single-chip microcomputer with on-board electrically-erasable programmable read-only memory which is write protected in several, separate blocks.

Abstract: A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.