Abstract: A system and method for remote power control across multiple distinct nodes of a logically coherent data processing system where each node has the design of a traditional standalone SMP server. The system is partitioned into two or more static partitions. Remote power control for the partition is achieved using a modified wake-on-LAN implementation in which magic packet filters on each NIC in the partition are modified to enable remote, partition-wide restart by a magic packet that is recognized by or common to all of the nodes. In one embodiment the wake-on-LAN filters of each NIC in the partition recognize and respond to magic packets addressed to any of the NIC's in the partition. In another embodiment, the wake-on-LAN filters of each NIC in the partition are modified to respond to a universal magic packet.

Abstract: A system and method for remote power control across multiple nodes of a partitioned data processing system. The system includes one or more nodes, each node including a chassis housing a traditional SMP server. The system may be partitioned into two or more SPAR's. Partition management software provides out of band power control to an entire partition, regardless of the number of nodes in the partition. The partition management code installed on each node of the partition is enabled to broadcast a power-on request to each of the nodes in the partition. Thus, when any service processor receives a power-on request, that service processor will resend the power on request to the broadcast group, thereby causing all of the nodes in the SPAR to power up. The broadcast packets may be routed to the other nodes via an out-of-band or private management LAN.

Abstract: A system includes a data processing core coupled to a system memory employing error correction code (ECC) circuitry. The core includes an indicator of when a correctable system memory error occurs and what address is associated with the error. A watchdog timer is instantiated on a system management device. Periodically, the timer prompts the management device to interrupt the processor and poll the error indicator to determine if a memory error has been detected. If an error is detected, the corresponding physical memory address is recorded. If a predetermined number of consecutive errors associated with a single memory address or range of addresses occurs, an alert is issued. In one embodiment, polling the error indicator is infrequent initially. As additional errors are detected, the polling frequency increases. At higher polling frequencies, the system may require a greater number of consecutive errors before taking additional action.

Abstract: A data processing system suitable for transmitting and receiving data packets via a network including a first processing entity and a second processing entity both having access to system memory data subject to transmission over the network after being formatted according to a network communication protocol. The first processing entity performs a first portion of the network communication protocol, such as a flow control portion, while the second processing entity performs a second portion of the protocol, such as acknowledgement handling or data retrieval. The first processing entity is typically a central processing unit of a network server while the second processing entity is typically a network communication device. The first and second processing entities may reside on a single physical system or on physically distinct systems connected via a switched bus I/O architecture.

Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

Abstract: A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

Abstract: A system and method for establishing and maintaining date information associated with an electronic device. The system is typically configured to prompt a user to enter or otherwise establish a valid date at some point after power is applied to the system. After establishing a valid date, the real time clock is configured to maintain real-time date/time information. Upon determining that a valid date has been set, the system may subsequently obtain date/time information from the real time clock and store the obtained date and time in the non-volatile memory as the in-service date. The system may be enabled to determine if, subsequent to establishing an in-service date, the user altered the date/time information in a manner that indicated an intent to extend the warranty period beyond the manufacturer specified warranty period.

Abstract: A multi-host data processing network and associated method are disclosed. The network includes a local host, a remote host, and a terminal including a display, a keyboard, and a pointing device. A display server associated with a user of the terminal is present on the local host. The display server enables the user to execute GUI applications on local and remote hosts from the terminal via a display server authorization mechanism. The network is configured to enable the user to execute a command entered at the terminal on the remote host using the display server as an intermediary. In one embodiment, the local host includes a client application and the remote host includes a daemon process, wherein the client application is enabled to receive the command from the user and the daemon process is configured to retrieve and execute the command.

Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

Abstract: A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.

Abstract: A photomask and a method for making the same in which an opaque feature (38) is formed on a transparent substrate (32) and a depression (44) is etched in the transparent substrate (32) adjacent to the opaque feature (38). The depression (44) is etched to a depth such that a phase difference between light passing through the substrate (32) outside the depression (44) and light passing through the depression is 180°. In one embodiment, the depression (44) is formed in the substrate directly adjacent to an edge of the opaque feature (38). In another embodiment, the depression (58) surrounds a mesa structure (59) formed in the substrate (50), and the opaque feature (62) resides on the mesa structure (59). The depression (58) may be laterally spaced from an edge of the opaque feature (62).

Abstract: A system for storing and configuring CMOS setting information remotely in a sewer blade environment includes a management module having includes persistent storage containing a table of CMOS setting information for each server blade. Each server blade includes boot block software that executes when the blade is booted. The boot block software initiates communication with the management module and retrieves its CMOS settings from the table. Thus, CMOS settings for a particular blade location remain unchanged each time a blade is replaced or upgraded. The management module and saver blades may implement a programming interface tat includes command abstractions for each CMOS setting. The management module sends command abstractions to each sewer blade during the CMOS configuration process. The server blade interprets the commands and maps the commands to specific CMOS bit addresses thereby making the specific CMOS implementation employed by any server blade transparent to the management module.

Abstract: An assembly for housing a power supply unit within a data processing system includes a carrier bracket for attaching to the power supply unit, a housing tray to engage the bracket moveably and define a size adjustable space for receiving the power supply unit, and a baffle hinged to the tray. The baffle covers a portion of the space and is moveable relative to the tray. The bracket and tray include complementary slide tracks enabling the bracket to moveably engage the tray. The baffle is hinged via pivot points engaged in baffle tracks in two of the tray sidewalls. The baffle may define a first gap between a hinged edge of the baffle and a sidewall of the tray and a second gap between a distal edge of the baffle and the bracket face plate. The baffle may include a plurality of extendible baffle plates to alter the baffle dimensions.

Abstract: A system, method, and computer program product for locating an audio segment includes an input device for transmitting an input sample indicative of the audio segment and a media player for playing audio information stored on the storage device. The system further includes a sample converter to generate a digitized representation of the input sample and a digitized representation of the audio information on the storage device. The digitized representation of the input sample may include a diphthong sequence indicative of the diphthong components of the input sample. In this embodiment, an audio converter of the system generates an audio content diphthong sequence. The system may further include a comparator configured to detect a match between the input sample diphthong sequence and a portion of the audio content diphthong sequence.

Abstract: A data processing system in which standard communication resource facilities are used to enable direct communication to a system management facility. In one implementation, the management adapter shares a communication resource, such as a serial port, with the host system. An arrangement of multiplexers is capable of connecting the local system to the shared resource, the management adapter to the shared resource, or the host system to directly to the management adapter. The host system includes a device driver for the shared resource. The shared resource device driver is leveraged to communicate to the management adapter using a standardized serial protocol (in the case of a shared serial port) when the multiplexers connect the system to the management adapter.

Abstract: A power-aware, logically partitioned data processing system and corresponding method of use include a set of physical resources and a hypervisor. The hypervisor creates partitions and allocates at least some of the physical resources to the partitions. The system further includes means for reducing the power consumption of any physical resources not allocated to a partition. The hypervisor may allocate physical resources to the partitions to maximize the number of unallocated physical resources. The physical resources may include processors and the hypervisor may allocate a fractional portion of at least one processor to a partition. In this embodiment, the system may reduce power consumption by scaling the supply voltage or clocking frequency to the fractionally allocated processor. The resources may include memory modules and the hypervisor may dynamically reduce the allocated memory and power consumption by minimizing the number of memory modules needed to support the memory allocated to the partitions.

Abstract: A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.

Abstract: A system and method for transferring information a data processing network. A client device suitable for connecting to the network includes a client application configured to receive information from the network and to present the received information to a user as audio information. The server is configured to provide information to the client data processing device responsive to the client request. The system is configured to determine when at least a portion of the information provided by the server is unsuitable for presentation by the client and to respond to the determination by storing the information for later access by the user, presenting a visually enhanced version of the information to the user, or providing portions of the information suitable for audio presentation to the user.

Abstract: The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a property during N time steps of its operation. The value of N is recorded and propagated. The propagated value of N is used to reduce resources expended during subsequent analysis of the integrated circuit by ignoring the model's adherence to the property during the early stages of subsequent analysis (during time steps less than N). The system may include a diameter estimator that identifies a value of N beyond which subsequent modeling of the integrated circuit produces no new states. Property checking is ignored during states having a time step value greater than the estimated diameter.