Abstract: In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.
Type:
Grant
Filed:
May 26, 2005
Date of Patent:
May 18, 2010
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Marcel ter Book, Peter J. Hopper
Abstract: The invention relates to a camera for generating digital images with an image sensor that is configured to convert an image formed by a lens into electronic signals. The digital camera is characterized by that the image sensor is attached to a movement element with a controllable drive, the movement element rendering the image sensor tiltable so that an angle between the axis of the lens and a plane of the image sensor is modifiable.
Abstract: In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.
Type:
Grant
Filed:
March 21, 2007
Date of Patent:
October 20, 2009
Assignee:
National Semiconductor Corporation
Inventors:
Weiye Lu, Elroy M. Lucero, Khusrow Kiani
Abstract: In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy forming vias through the passivation layer overlying the top metal layer and forming metal interconnects.
Abstract: In a test system for a semiconductor device, the device under test (DUT) is remotely located relative to the tester that generates the test vector signals. The tester and remotely located DUT are connected by a serial connection and each includes a serializer-deserializer for converting outgoing data to serial form and deserializing incoming data.
Abstract: In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region next to the drain or an additional floating p-region next to the drain.
Abstract: In a lapping process for lapping away layers from a semiconductor device, where the region of interest is located near an edge or corner of the device, the method includes adding additional semiconductor material adjacent the region of interest.
Abstract: In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.
Type:
Grant
Filed:
August 31, 2005
Date of Patent:
July 1, 2008
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
Abstract: In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.
Type:
Grant
Filed:
August 4, 2005
Date of Patent:
May 20, 2008
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
Abstract: In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
Type:
Grant
Filed:
June 21, 2004
Date of Patent:
November 20, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
Abstract: In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.
Abstract: In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.
Type:
Grant
Filed:
August 10, 2002
Date of Patent:
October 23, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Pavel Poplevine, Annie-Li-Koow Lum, Hengyang Lin, Andrew J. Franklin
Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.
Type:
Grant
Filed:
August 14, 2006
Date of Patent:
September 11, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
Abstract: In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical force. One aspect of the invention includes making use of specifically chosen adhesives to secure the die to the die paddle and to each other, so that any subsequent removal can readily be achieved.
Abstract: In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric.
Type:
Grant
Filed:
April 12, 2002
Date of Patent:
July 24, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Sergei Drizlikh, Todd Patrick Thibeault, Thomas Francis
Abstract: In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.
Type:
Grant
Filed:
December 12, 2003
Date of Patent:
March 27, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Willem Kindt, Peter J. Hopper
Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.
Type:
Grant
Filed:
January 9, 2003
Date of Patent:
March 20, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Ann Concannon, Peter J Hopper, Marcel ter Beek
Abstract: In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.
Type:
Grant
Filed:
December 17, 2004
Date of Patent:
February 20, 2007
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski, Philipp Lindorfer
Abstract: In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs are formed in a p-well which, in turn, is formed in a n-well. Each dual polarity input is isolated by a PBL under the p-well, and a NISO underneath the n-well. An isolation ring separates and surrounds the inputs. The isolation ring comprises a p+ ring or a p+ region, n+ region, and p+ region formed into adjacent rings.
Type:
Grant
Filed:
December 12, 2003
Date of Patent:
December 5, 2006
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
Abstract: In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers.