Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.
Type:
Grant
Filed:
October 31, 2002
Date of Patent:
March 16, 2004
Assignee:
National Semiconductor Corporation
Inventors:
Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer, Andy Strachon, Peter Johnson
Abstract: In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.
Abstract: In a capacitive structure of an integrated circuit a comb-like configuration or other thin element configuration provides for capacitive coupling between electrode elements in one plane. By forming electrodes in a plurality of planes and selectively shifting the positioning of the electrodes in one plane relative to those in another plane, capacitive coupling between the electrodes in the different planes is achieved. In this way capacitance and stability with process variations can be affected. Furthermore, by using the metal interconnect layers to form the capacitive structures, the need for additional process steps in defining poly-layers, is avoided.
Abstract: In an ESD protection device and method, greater stability is achieved in a MOS device by replacing the thin gate oxide with a shallow trench isolation region, and breakdown voltages are reduced by providing for dynamic substrate control. In the case of NMOS, the dynamic substrate control also has the effect of reducing triggering voltage.
Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a reverse-coupled NPN BJT acting as an avalanche diode is adjusted to comply with breakdown voltage and latchup requirements by including a resistor between the base and collector of the BJT.
Abstract: A liquid dispenser comprises a container for supporting liquid, and has a dispensing end with an opening. A reservoir is located in the container and is connected to the opening, and a structure is provided for channeling liquid into the reservoir. Liquid is propelled from the dispenser by squeezing resiliently depressable portions of the dispenser. The reservoir may take the form of a bowl-like structure or may retain liquid by cohesive and adhesive forces. The dispenser may also include a nozzle and a rest for resting the dispenser against a suitable surface when squeezing the dispenser.
Type:
Grant
Filed:
July 17, 2000
Date of Patent:
May 14, 2002
Inventors:
Klaus M. A. Vollrath, Jurgen K Vollrath