Patents Represented by Attorney Kacvinsky LLC
  • Patent number: 7516342
    Abstract: Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, Jose Allarey, Eric Heit
  • Patent number: 7512070
    Abstract: Various embodiments are described to adaptively use a transmit opportunity. A wireless system comprising a memory and a processor is described. The processor is coupled to the memory. In one embodiment, the processor allocates a first portion of a transmit opportunity for an initial data burst and the processor allocates a second portion of the transmit opportunity for other operations including retries.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventor: Adrian P. Stephens
  • Patent number: 7512711
    Abstract: A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded together. According to one embodiment, the plurality of network units comprise a plurality of content based message directors, each to route or direct received messages to one of a plurality of application servers based upon the application data in the message. According to another embodiment, the plurality of network units comprise a plurality of validation accelerators, each validation accelerator to validate at least a portion of a message before outputting the message.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: March 31, 2009
    Inventors: John B. Abjanic, David A. Marlatt, John A. Malo
  • Patent number: 7509347
    Abstract: System, apparatus, method, and article for techniques to associate media data with related information. A mobile computing device includes a media manager module. The media manager module processes a media file including metadata. The media manager module retrieves a first content from a metadata field in the metadata. The media manager module retrieves a second content from a field in an application file associated with an application client. The media manager module compares the first and second contents and determines whether the first and second contents are associated. If the first and second contents are associated, the media manager module retrieves the second content and inserts the second content in a second metadata field of the media file.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 24, 2009
    Assignee: Palm, Inc.
    Inventor: Paul Chambers
  • Patent number: 7506267
    Abstract: Embodiments of the present invention blend frames over a specified temporal window to produce a smooth appearance at a reduced frame rate. As the window moves further or closer to the viewer, motion blur may be accomplished by temporal averaging. In particular, the temporal average is used to blend image information for a predefined/brief interval before and after the time of the output frame, retaining all of the image information, but in a slightly blurred form. After the relevant image information is retained, frames may be displayed at a reduced output rate while retaining sufficient information to reproduce a smoothly moving animation sequence.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Philip J. Corriveau, Thomas E. Walsh
  • Patent number: 7504856
    Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Alex Waizman, Marcelo Yuffe, Ziv Shmuely
  • Patent number: 7506239
    Abstract: Apparatus, system, and method for scalable traceback techniques for channel decoding are described.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: March 17, 2009
    Inventors: Raghavan Sudhakar, Ravi Kolagotla
  • Patent number: 7502602
    Abstract: Briefly, according to embodiments of the invention, there is provided a method and an apparatus to compensate for a closed loop response error of a transfer function of a phase locked loop unit.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventor: Guy Wolf
  • Patent number: 7502630
    Abstract: The invention includes a method and system for wirelessly transmitting data between a base transceiver station and a subscriber unit. The method comprises generating control signals to configure a base transceiver station to transmit selected data streams to a corresponding subscriber unit on an assigned channel of a multiple access protocol, transmitting in response to the control signals and in a spatially separate fashion, the selected data streams on the assigned channel of the multiple access protocol and utilizing co-located electric dipole and magnetic dipole antennae at the subscriber unit to receive the selected data streams.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventor: John Fan
  • Patent number: 7502920
    Abstract: The present invention, generally speaking, provides a hierarchy of configuration storage. The highest level of the hierarchy is an active configuration store; the lowest level is an off-chip configuration store; in between are one or more levels of configuration stores. Every configuration is promoted from the lowest off-chip level, through each level, up to the highest active level. Each ascending level of the hierarchy has a decreasing latency time required to promote a configuration to the next higher level of the hierarchy, and a decreasing amount of available storage. This separation into levels allows the amount of available storage to be adjusted depending on the inherent latency of the level's storage mechanism, where a longer latency requires a larger cache. This in turn allows the total required storage for a given performance level to be minimized.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Christopher E. Phillips, Dale Wong
  • Patent number: 7499274
    Abstract: In some embodiments, a method, apparatus and system are described for enhancing an enclosure of a device, such as a computing device. The system may include a frame and an apparatus, wherein the apparatus includes the enclosure, which may form a cover of a computing device, and a base. In some embodiments, the enclosure may be composed of materials with different thermal properties when compared to the base. In some embodiments, the enclosure may include vents or openings of various configurations. In some embodiments, the base may be a heat spreader or a heat sink. Other embodiments may be described.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventors: Scott Noble, Seri Lee
  • Patent number: 7499215
    Abstract: A first panel includes an optically transmissive body having a front side and a rear side. The body has a width, a height, and a depth. The depth is substantially less than either of the width or the height. The body includes a first edge on a first side defining a first tongue protruding outwardly from the first edge. The body includes a second edge on a second side defining a first groove recessed within the second edge. The first tongue is adapted to couple to a corresponding groove and the first groove is adapted to couple to a corresponding tongue. A first optical film is coupled to the front side of the body.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventor: Paul S. Levy
  • Patent number: 7496095
    Abstract: Each host/node in a network includes a protocol stack (such as TCP/IP), a host channel adapter (HCA) to interface the host to a local network or fabric, and a LAN Emulation (LANE) driver for emulating a LAN network to the protocol stack. Each host in the local network is assigned a global (or legacy) physical address (e.g., a IEEE 802.3 Ethernet MAC address or the like) and a network address (such as an IP address). In addition, the LANE driver maps the global (or legacy) physical address to the local physical address. According to an embodiment, the local physical address is embedded within the global (or legacy) physical address to avoid the use of a specialized ARP protocol. A connection oriented virtual interface (VI) channel is established between a first node and each of the other nodes in the network. The HCA maps the local physical address (e.g., local MAC address) of another node to the VI channel used to communicate with the other node.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventor: Arlin R. Davis
  • Patent number: 7492317
    Abstract: Apparatus, system, and method are described for a complementary metal oxide semiconductor (CMOS) integrated circuit device having a first metal layer that includes a radiating element and a second metal layer that includes a first conductor coupled to the radiating element. The first conductor and the radiating element are mutually coupled to form an antenna to wirelessly communicate a signal.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Keith R. Tinsley, Seong-Youp Suh
  • Patent number: 7489621
    Abstract: Various embodiments are described for adaptive puncturing techniques involving an adaptive bit loading block to select a modulation scheme and a puncturing pattern for each of a plurality of subcarriers or subcarrier bands based on subcarrier channel state information.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 10, 2009
    Inventors: Alexander A Maltsev, Ali S. Sadri, Alexei V. Davydov
  • Patent number: 7486279
    Abstract: A device and system are disclosed. In one embodiment the device comprises a primary display unit, a base unit coupled to the primary display unit, and a touch-sensitive secondary display unit, coupled to the base unit, operable to receive input from a user and display information for the user.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Hong W. Wong, Wah Yiu Kwong, Hue V. Lam
  • Patent number: 7482857
    Abstract: A circuit provides a bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: January 27, 2009
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Patent number: 7480189
    Abstract: A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Jay B. Miller
  • Patent number: 7477228
    Abstract: An approach to controlling an electronic system display includes determining a latency associated with changing a backlight brightness from a first level to a second level, and based on the determined latency, providing the latency predictions to a coordinating entity, which adjusts the backlight brightness and image luminance to occur in such a manner so as to substantially avoid associated visually disturbing artifacts which would otherwise occur if the two actions were applied asynchronously.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 13, 2009
    Assignee: Intel Corporation
    Inventor: David A. Wyatt
  • Patent number: 7472289
    Abstract: An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Jorge P. Rodriguez, Leslie E. Cline, Barnes Cooper