Abstract: An optical test head comprises one or more detectors for providing output signals indicative of the condition of a workpiece surface. Data from these detectors are stored in one or more memories only when the data from the detectors satisfy one or more conditions (e.g. the data exceed than a particular threshold). The data are then passed from the one or more memories to an electrical circuit for processing. In addition, location information is stored in one or more memories and passed on to the electrical circuit when the data from the detectors satisfy the one or more conditions.

Abstract: An optical test head comprises one or more optical input paths by which a beam of light is communicated from a light source to a workpiece and one or more optical output paths by which light reflected off of the workpiece is communicated to a detector. The input optical path and the output optical path can include one or more mirrors and one or more lenses. At least one of the optical paths includes a layer for trapping and/or absorbing stray light. One or more of the lenses includes an anti-reflective coating for reducing noise caused by unwanted light reflection off of the lenses. The optical paths include one or more masks reducing stray light. The one or more masks can have an adjustable aperture (e.g. an iris).

Abstract: A method for manufacturing a magnetic disk comprises the steps of depositing NiP (20) on a substrate (22); depositing NiNb (24) on the NiP; and laser texturing the NiNb. "Sombrero" shaped texture features are more easily formed on the substrate/NiP/NiNb structure than a substrate/NiP structure. The disk is completed by depositing an underlayer (e.g. sputtered Cr or NiP), a magnetic layer (e.g. a Co alloy) and a protective overcoat (e.g. by hydrogenated carbon).

Abstract: A method for texturing a glass ceramic substrate comprising the steps of applying a laser pulse to the substrate such that a portion of said substrate is heated to a temperature higher than the glass transition temperature of the glass phase of said substrate but lower than the melting point of the crystal phase of said substrate.

Abstract: A method of producing a high resolution expanded analog gray scale mask is described. Using an inorganic chalcogenide glass, such as a selenium germanium, coated with a thin layer of silver, a gray scale mask may be produced with accurate control of the size, uniformity and variance of the pixels. The selenium germanium glass is composed of column structures arranged perpendicularly to the substrate giving a possible edge precision of 100 .ANG.. The column structures also prevent undercutting during the etching process, thus permitting pixels to be placed close together. Accordingly, selenium germanium may be used as a high resolution gray scale mask with an expanded analog gray scale. The gray scale mask may be used to impress information as a modulated thickness on a selenium germanium photoresist layer on an inorganic substrate. The selenium germanium photoresist layer may then transfer the gray scale to the substrate.

Abstract: A method of producing a high resolution expanded analog gray scale mask is described. Using an inorganic chalcogenide glass, such as a selenium germanium, coated with a thin layer of silver, a gray scale mask may be produced with accurate control of the size, uniformity and variance of the pixels. The selenium germanium glass is composed of column structures arranged perpendicularly to the substrate giving a possible edge precision of 100 .ANG.. The column structures also prevent undercutting during the etching process, thus permitting pixels to be placed close together. Accordingly, selenium germanium may be used as a high resolution gray scale mask with an expanded analog gray scale. The gray scale mask may be used to impress information as a modulated thickness on a selenium germanium photoresist film on an inorganic substrate. The selenium germanium photoresist film may then transfer the gray scale to the substrate.

Abstract: In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

Abstract: A speedometer is provided for determining speed by providing a sound signal at a first frequency, receiving a second signal which is the reflection of the first signal, and determining difference in frequency between the first and second signals created by the Doppler Effect. A speech synthesis chip within the speedometer provides a verbal indication of velocity. In this way, a person using the provided speedometer does not have to look at a dial or other visual indicator.Provided within the speedometer is a heat-sensitive transducer for measuring the air temperature. In this way, the speedometer can take into account the change in the speed of sound with respect to temperature when calculating velocity.

Abstract: A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate (16e, 16f). A layer of silicon dioxide (20) is then formed on the gate. A second mask (22) defines the gate contact region (window 22a)) as well as where a deep body region (24) is to be formed (window 14a)). Portions of the gate insulation layer not covered by the gate are subsequently removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the gate. A conductive layer 30 is patterned, thereby leaving a gate contact and a source and body contact. A passivation layer 34 is then patterned, thereby defining bonding pads. Of importance, the above-described process uses only 4 photolithographic masking steps.

Abstract: One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.

Abstract: A method for manufacturing a disk includes the step of forming a first nickel-phosphorus alloy layer on an aluminum substrate, e.g., by electroless plating. A second nickel-phosphorus layer is then sputtered onto the first nickel-phosphorus layer, and a magnetic alloy is sputtered onto the second nickel-phosphorus layer. The magnetic alloy is typically sputtered immediately after the second nickel-phosphorus layer is formed without removing the disk from the sputtering apparatus between the time the second nickel-phosphorus layer is formed and the time the magnetic alloy is formed. Because of this, contaminants are not capable of lodging on or affecting the surface of the disk prior to formation of the magnetic alloy. The second nickel-phosphorus layer is typically amorphous and therefore masks any nonuniformities in the surface of the first nickel-phosphorus layer.

Abstract: An improved mouse includes a stylus and a base. Transducers in the stylus detect motion of the mouse relative to a surface. In this way, the stylus can be used as a pen-shape mouse or inserted into the base, which can then be operated as a more conventional mouse.

Abstract: An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.

Abstract: A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.

Abstract: A Zener diode (D) exhibiting subsurface breakdown includes a cathode (36) formed entirely within the emitter (22, 28) of a vertical PNP transistor (Q). The base (16) and collector (11) of the PNP transistor are resistively coupled to ground. The emitter of the PNP transistor functions as the anode of the Zener diode. Because of this, it is unecessary to provide an emitter contact. The PNP transistor compensates for changes in Zener breakdown voltage caused by changes in temperature. Because the PNP transistor is formed directly underneath the Zener diode, the temperature of the PNP transistor accurately tracks that of the Zener diode and therefore provides better temperature compensation. Also, because the cathode of the Zener diode is formed directly in the emitter of the PNP transistor, there is no lateral current flow and attendant voltage drop in the emitter of the PNP transistor.

Abstract: A circuit for protecting an input MOS FET (Q1) from electrostatic discharge pulses includes a plurality of diodes (D112a through D112f) coupled to the bonding pad (102) of an integrated circuit via a plurality of resistors (R110a through R110f). The resistors prevent excessive current from flowing through and hence damaging any of the diodes. The diodes possess a unique shape which maximizes the perimeter to surface area ratio and therefore permits more efficient energy dissipation along the periphery of the diodes. The diodes are adapted to break down in response to an excessive voltage at the bonding pad and therefor protect the gate structure of the input transistor. Also included in the circuit is a protective bipolar transistor (Q2) having a collector coupled to the bonding pad, an emitter coupled to ground and a base resistively coupled to ground.

Abstract: A field effect transistor includes a source region, a drain region, and a channel region formed in a semiconductor substrate and a floating gate and a control gate formed over the substrate. An opaque cover (typically aluminum) is formed over but electrically insulated from the transistor to prevent light from striking and affecting the electrical charge on the floating gate. The periphery of the opaque cover ohmically contacts the semiconductor substrate, thereby limiting the amount of light reaching the floating gate, except where the source and drain extend inwardly beyond the periphery of the opaque cover. The control gate extends over a portion of the substrate surrounding the transistor, and helps hinder light from reaching the floating gate. In addition, semiconductor material formed concurrently with the control gate extends over the source and drain regions, thereby providing additional shading.

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.

Abstract: A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration. The same pins can be used for both configuration and user logic. Also signals such as chip enable and other control signals can be modified by user logic before performing their function so that chips external to the FPGA can be eliminated. Upon power-up of the chip, each programmable switch connects its pad to the programming logic which programs configuration memory, so that the programming logic can receive instructions from an external source and control programming of the core logic of the chip. The configuration memory programs not only the internal circuitry accessed by the user but also the programmable switch itself.

Abstract: A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.