Patents Represented by Attorney, Agent or Law Firm Kenneth E. Leeds
  • Patent number: 4749459
    Abstract: A film of magnetic recording media is formed by sputtering an alloy of cobalt and platinum onto a substrate. The sputtering takes place in a chamber containing argon and nitrogen. The magnetic coercivity of the resulting film is controlled by varying the concentration of nitrogen in the sputtering chamber. By using this technique, the film coercivity is controlled without varying other important parameters such as the saturation magnetization.
    Type: Grant
    Filed: March 10, 1986
    Date of Patent: June 7, 1988
    Assignee: Komag, Inc.
    Inventors: Tsutomu T. Yamashita, Ching-Cheng Shir, Tu Chen
  • Patent number: 4740485
    Abstract: A method for forming a titanium tungsten fuse begins with the steps of forming a silicon dioxide layer (42), a titanium tungsten layer (44) and a aluminum layer (46) on a silicon substrate (40). The titanium tungsten layer serves as fuse material while the aluminum layer serves as interconnect material. A photolithographic mask (48) is then applied to the wafer. The portion of the aluminum layer exposed by the photolithographic mask and the portion of the titanium tungsten layer lying thereunder are then removed. Because both the aluminum and titanium tungsten layers are etched simultaneously, a dry etching process can be used during this step. The resulting structure includes a thin aluminum and titanium tungsten region where the resulting fuse is to be formed. Thereafter, the first photolithographic mask is removed and a second photolithographic mask is applied to the wafer which includes a window region where the titanium tungsten fuse is to formed.
    Type: Grant
    Filed: July 22, 1986
    Date of Patent: April 26, 1988
    Assignee: Monolithic Memories, Inc.
    Inventor: Bradley A. Sharpe-Geisler
  • Patent number: 4721682
    Abstract: A structure for isolating a bipolar transistor (100) from an adjacent transistor includes a first silicon dioxide isolation region (110) laterally surrounding the transistor and a conductive channel stop region (112) laterally surrounding the silicon dioxide isolation region. The channel stop region allows electrical potential of the substrate (102) to be controlled and the silicon dioxide isolation region prevents the channel stop from contacting the transistor.
    Type: Grant
    Filed: September 25, 1985
    Date of Patent: January 26, 1988
    Assignee: Monolithic Memories, Inc.
    Inventors: Scott O. Graham, Lawrence Y. Lin, Hua T. Chua
  • Patent number: 4717833
    Abstract: Each of a plurality of parallel connected power supplies is controlled by a parallel control circuit which measures the output current from each power supply and compares this output current to the average output current produced by all the power supplies and generates a signal representative of the difference therebetween to drive the output current of the power supply toward the average output curent from all power supplies. The structure includes in addition a switch for disconnecting the parallel control circuit of a failed power supply from the system and a booster resistor for assisting in bootstrapping the startup of a given power supply being inserted into parallel with the preexisting parallel connected power supplies.
    Type: Grant
    Filed: May 19, 1986
    Date of Patent: January 5, 1988
    Assignee: Boschert Inc.
    Inventor: Kenneth T. Small
  • Patent number: 4712044
    Abstract: An array of indicator lamps is mounted on the rear of an automobile for signaling turns. When a turn is signaled, the lamps turn on in sequence, thereby creating the impression of motion in the desired direction. Each lamp is coupled to a battery via an associatd relay switch. A control circuit closes the relay switches in sequence, thereby turning on the lamps in sequence. The control circuit includes a set of flip-flops, each relay switch closing in response to an associated one of the flip-flops, which change state in response to a clock signal.
    Type: Grant
    Filed: December 17, 1985
    Date of Patent: December 8, 1987
    Inventor: Mark S. Phillips
  • Patent number: 4708919
    Abstract: A process for manufacturing a mask for use in X-ray photolithography begins with a step of providing a glass disk (50) which is coated with a layer of boron nitride (52). The glass disk is about 1/4 of an inch thick and about 4.5 to 6 inches in diameter. A circular portion (50a) of the boron nitride layer on one side of the glass disk is removed thus exposing a circular portion of the glass disk. The exposed portion of the glass disk is then removed, leaving a glass ring coated with a boron nitride membrane on one side. A layer of polyimide (54) and a layer of x-ray opaque substance (58) is deposited on the boron nitride membrane. The x-ray opaque substance is then patterned, the resulting structure being a mask which is used in X-ray photolithography.
    Type: Grant
    Filed: August 2, 1985
    Date of Patent: November 24, 1987
    Assignee: Micronix Corporation
    Inventors: Alexander R. Shimkunas, James J. LaBrie
  • Patent number: 4707909
    Abstract: A process of providing semi-insulating thin film resistors with closer tolerance values by furnance-annealing the film to increase is resistance to less than the final intended value, and then focused heat source-annealing the film to within a close tolerance of the final intended value.
    Type: Grant
    Filed: August 8, 1986
    Date of Patent: November 24, 1987
    Assignee: Siliconix Incorporated
    Inventor: Richard A. Blanchard
  • Patent number: 4701695
    Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.
    Type: Grant
    Filed: February 14, 1986
    Date of Patent: October 20, 1987
    Assignee: Monolithic Memories, Inc.
    Inventors: Albert Chan, Mark Fitzpatrick, Don Goddard, Robert J. Bosnyak, Cyrus Tsui
  • Patent number: 4701057
    Abstract: A linear motion rolling contact bearing assembly includes a slider unit having a main body, in which a pair of endless circulating paths for rolling members is formed, and a U-shaped frame, and having a rail extending over a predetermined length and having a U-shaped cross section for slidably receiving therein the slider unit. An end mounting section for mounting to an exterior member outside of the assembly is formed at least at one end of the U-shaped rail and/or the U-shaped frame. Thus, any deformation and/or distortion, which may be produced when mounting the assembly to an apparatus, is prevented from being transmitted to the remaining part of the assembly, thereby maintaining a high dimensional precision and structural integrity.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: October 20, 1987
    Assignee: Nippon Thompson Co., Ltd.
    Inventor: Yoshihiro Kashiwabara
  • Patent number: 4701058
    Abstract: A linear motion rolling contact bearing assembly including a rail, a slider and a plurality of rolling members interposed between the rail and the slider for providing a rolling contact therebetween is provided. The rail includes a bottom wall and a pair of side walls extending upward from the opposite sides of the bottom wall, so that the rail has a U-shaped cross section. The slider includes a frame which is comprised of a top wall and a pair of side walls depending from the opposite sides of the top wall, so that the frame has a U-shaped cross section. Each of the side walls is provided with a guide groove so that the rolling members are interposed between the rail and the slider as partly fitted in a pair of associated guide grooves.
    Type: Grant
    Filed: August 20, 1986
    Date of Patent: October 20, 1987
    Assignee: Nippon Thompson Co., Ltd.
    Inventor: Tatsuo Mottate
  • Patent number: 4698617
    Abstract: The present apparatus provides for the encoding of data carried on bus lines running between integrated circuits in order to protect the data carried upon those bus lines, with encoding and decoding circuits included for providing those functions in regard to the data on the bus lines.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: October 6, 1987
    Assignee: American Microsystems, Inc.
    Inventor: Jerry R. Bauer
  • Patent number: 4696878
    Abstract: An additive process for manufacturing a mask (113) used in x-ray photolithography includes the step of coating a boron nitride layer (102) with a layer of indium tin oxide (104) and a second layer of boron nitride (106). The second boron nitride layer is patterend and used as a stencil during a plating process while the indium tin oxide layer is used as a plating base. Because boron nitride and thin indium tin oxide are both x-ray transparent, neither the stencil nor the plating base need be removed during the manufacturing process.
    Type: Grant
    Filed: August 2, 1985
    Date of Patent: September 29, 1987
    Assignee: Micronix Corporation
    Inventor: Alexander R. Shimkunas
  • Patent number: 4694389
    Abstract: A transformer for use in a power converter includes first and second primary windings tightly coupled to a first secondary winding, and third and fourth primary windings tightly coupled to a second secondary winding. Of importance, the first and second primary windings are only loosely coupled to the third and fourth primary windings. In one embodiment of the invention, the transformer includes a plurality of legs. The first and second primary windings and the first secondry winding are wound around one half of one of the legs but not a secnd half of the one leg. The third and fourth primary windings and the second secondary winding are wound around the second half of the one leg but not the first half. In another embodiment of the invention, the transformer includes a U core. The first and second primary windings and the first secondary winding are wound around a first leg of the U core while the third and fourth primary windings and the second secondary winding are wound around a second leg of the U core.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: September 15, 1987
    Assignee: Boschert, Incorporated
    Inventor: Kenneth T. Small
  • Patent number: 4684830
    Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: August 4, 1987
    Assignee: Monolithic Memories, Inc.
    Inventors: Cyrus Tsui, Andrew K. L. Chan, Albert Chan, Mark E. Fitzpatrick, Zahid Ansari
  • Patent number: 4682405
    Abstract: A transistor is provided which includes an electrical contact (122) formed in a V-shaped groove (118). Because of the unique shape of the electrical contact, a smaller surface area is required for its formation thus rendering it possible to construct a transistor having a smaller surface area. The groove is formed by anisotropically etching an expitaxial layer (102) on a semiconductor substrate (100) using, for example, KOH.
    Type: Grant
    Filed: July 22, 1985
    Date of Patent: July 28, 1987
    Assignee: Siliconix Incorporated
    Inventors: Richard A. Blanchard, James D. Plummer
  • Patent number: 4680243
    Abstract: A method for manufacturing a mask (100) for use in x-ray photolithographic processes includes the step of coating a silicon wafer (10) with a layer of boron nitride (12). A masking substance (14) is used to coat one side of the boron nitride coated wafer, and the boron nitride is etched off of the other side of the wafer. The wafer (10) is then bonded to a pyrex ring (16) using a field assisted thermal bonding process. During the field assisted thermal bonding process, the silicon (11) is bonded directly to the pyrex (16). Then, a zirconium layer (24) is used to cover the mask and is selectively etched where it is desired to remove a circular portion of the silicon. Thereafter the silicon is subjected to a semianisotropic etch. The remaining structure includes a pyrex ring bonded to a silicon ring across which a layer of boron nitride is stretched. The layer of boron nitride is subjected to an annealing process and is then coated with an x-ray opaque material.
    Type: Grant
    Filed: August 2, 1985
    Date of Patent: July 14, 1987
    Assignee: Micronix Corporation
    Inventors: Alexander R. Shimkunas, Barry Block
  • Patent number: 4677391
    Abstract: A series biasing arrangement for a pair of junction field effect transistors (JFETs), which may be used in RF amplifiers, mixers or oscillators, comprises connecting the JFETs together in series, with the gates of the two JFETs selectively connected to different reference potentials. The first FET is also connected to the DC voltage source. In one embodiment of the invention, two operational amplifiers, whose output leads are connected to the gates of corresponding JFETs have their noninverting input leads connected to selected points on a voltage divider made up of three resistors and their inverting input leads each connected to the source of a corresponding JFET. The drain to source voltage drops across the JFETs are controlled solely by the values of two of the resistors in the three resistor voltage divider. The bias current through the series-connected JFETs can be controlled independently of the drain to source voltage drops across each of the JFETs.
    Type: Grant
    Filed: May 9, 1986
    Date of Patent: June 30, 1987
    Assignee: Microwave Technology, Inc.
    Inventor: Kenneth Kawakami
  • Patent number: 4674020
    Abstract: A power supply (100) includes a first lead (12) for receiving an input voltage (Vin) and an inductor (L1) and a switching transistor (Q1) coupled in series between the input lead and ground. The node (N1) between the inductor (L1) and switching transistor (Q1) is coupled through a diode (D1) to an output terminal (14). When the switching transistor is on current flow causes energy to be stored in the inductor. When the switching transistor turns off, the energy stored in the inductor is provided to a load (RL) coupled to the output terminal. The on-time of the transistor is controlled by a comparator (20) which receives a first voltage (V3) proportional to the current through the switching transistor and a second voltage (V4). The second voltage decreases linearly with respect to time at a rate dependent on the difference between the voltage at the output terminal (Vout) and a reference voltage (Vref).
    Type: Grant
    Filed: December 13, 1985
    Date of Patent: June 16, 1987
    Assignee: Siliconix Incorporated
    Inventor: Lorimer K. Hill
  • Patent number: 4671850
    Abstract: A process for manufacturing a mask for use in x-ray photolithography starts with the step of coating the first and second sides of a silicon wafer (100) with a boron nitride layer (102). The first side of the wafer (100) is coated with a polyimide layer (104) which serves as a primary x-ray transparent layer for supporting a subsequently deposited x-ray opaque material. The first and second sides of the wafer (100) are then covered with a second boron nitride layer (106). The second side of the wafer (100) is then bonded to a support structure such as a pyrex ring (108). A portion of the first and second boron nitride layers (102, 106) is then removed thus exposing a portion of the underlying silicon substrate (101). The exposed portion of the silicon substrate is then removed thus leaving a ring which supports an x-ray transparent membrane comprising the first boron nitride layer (102), the polyimide layer (104) and the second boron nitride layer (106).
    Type: Grant
    Filed: August 16, 1985
    Date of Patent: June 9, 1987
    Assignee: Micronix Corporation
    Inventor: Alexander R. Shimkunas
  • Patent number: 4668336
    Abstract: A method of manufacturing a mask for use in x-ray photolithography includes the steps of coating a set of wafers (20) with boron nitride (22). The tension in the boron nitride is measured by using a capacitive probe (26) to measure bowing in a set of test wafers. The remaining wafers are attached to a pyrex ring (28), and the boron nitride is removed from one side of the wafers. A circular hole is then etched in the wafer, and a layer of tantalum (32) and gold (34) are formed on the remaining boron nitride membrane. The gold (34) is patterned via a sputter etching process. Power is reduced at the end of the sputter etching process slowly to reduce mechanical stress in the mask. The tantalum (32) is then etched via a reactive ion etching process. In this way, an x-ray transparent boron nitride membrane is used to support x-ray opaque gold.
    Type: Grant
    Filed: May 23, 1986
    Date of Patent: May 26, 1987
    Assignee: Micronix Corporation
    Inventor: Alexander R. Shimkunas