Abstract: The present invention provides methods and apparatus for rapid compression of images composed of pixels into high-resolutions, compressed icon images, and for dynamic fault imaging of operating faults in integrated circuit devices employing such methods. Displaying a plurality of such icons juxtaposed on a screen permits ready tracing of a fault in an IC device under test, even by persons having little knowledge of the functionality of the devices.In accordance with the invention, an image made up of n.times.n pixels may be compressed into an icon of p.times.p pixels, where n.dbd.P.multidot.q and q is an integer, by dividing the image into p tiles of q.times.q pixels, selecting q pixels from each tile, where each of said selected q pixels is representative of predetermined directional orientations within the tile, and calculating the mean value of the selected q pixels, to produce a single pixel representative of the tile. The pixels representative of said tiles thus form an icon of p.times.p pixels.

Abstract: A declarative object-oriented approach to menu construction provides a mechanism for specifying the behavior, appearance and function of menus as part of an interactive user interface. Menus are constructed from interchangeable object building blocks to obtain the characteristics wanted without the need to write new code or code and maintaining a coherent interface standard. The approach is implemented by dissecting interface menu behavior into modularized objects specifying orthogonal components of desirable menu behaviors. Once primary characteristics for orthogonal dimensions of menu behavior are identified, individual objects are constructed to provide specific alternatives for the behavior within the definitions of each dimension. Finally, specific objects from each dimension are combined to construct a menu having the desired selections of menu behaviors.

Abstract: An improved lead for surface-mounted electronic components is described. The improved lead includes an opening through the portion of the lead to be placed in contact with the printed circuit board for soldering. The opening, having a diameter approximately equal to the thickness of the lead, enables the detection of correctly-soldered joints using automated inspection equipment. When the lead is correctly soldered, solder is drawn by capillary action into the opening where it forms a meniscus. By automatically detecting the curvature of the meniscus, the quality of the solder joint may be determined.

Abstract: Methods and apparatus are disclosed for rapid and interactive "warping" of a first image made up of pixels to form a resulting image made up of pixels which are aligned, pixel-for-pixel, with a second image made up of pixels. The images may be stroboscopic voltage contrast images representing operating states of two integrated circuit devices--a failing device and a fully functional device. The aligned images permit an engineer who may have little knowledge of the device to diagnose dynamic failures of the failing device by comparing the aligned images to produce an image showing the differences.

Abstract: A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction.

Abstract: An acoustic method and apparatus for investigating an earth formation penetrated by a borehole are described. Acoustic transducers are mounted on a tool to accurately determine the distance between a segment of the tool and the wall of the borehole. The acoustic transducers are positioned in such manner that the stand-off distance between individual resistivity measuring electrodes in an array, which is also mounted on the tool segment, and the borehole wall can be measured. The stand-off measurement is recorded and may be used to correct the electrode resistivity measurements. In one embodiment a calibration of acoustic transducers as a function of depth is obtained by employing acoustic calibrating transducers to compensate for borehole environment effects on the performance of the acoustic transducers as well as determine the acoustic velocity of the borehole fluid, such as mud. Several embodiments are described.

Abstract: A multiple phase-splitter TTL tristate output circuit having a feedback diode coupled between the signal output and the collector of a first phase-splitter transistor to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential. An independent base drive is coupled to the base of the first phase-splitter transistor independent from any base drive coupled to the other phase-splitter transistor or transistors. Current hogging of the base drive current to the first phase-splitter transistor by the other phase-splitter transistors is thereby prevented. The first phase-splitter transistor which is coupled in the feedback circuit with the accelerating feedback diode to the base of the pulldown transistor element can therefore maintain the high current sinking mode through the pulldown transistor element with gain step-up proportional to .beta..sup.2 when the output is at the high voltage level.

Abstract: A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.

Abstract: TTL circuits are described for generating from an input signal complementary output signals useful in integrated circuit applications. For an enable gate, an alternate enable transistor element is coupled in emitter follower configuration in the enable gate with the base of the alternate enable transistor coupled to follow the enable gate input signal E and provide through the emitter circuit an alternate enable signal A complementary to the enable signal E. The complementary enable signals are applied in an improved TTL tristate output device with reduced output capacitance. The alternate enable signal A is coupled to the base of an active discharge transistor element at the base of the pull-down transistor of the tristate input device for actively discharging and diverting Miller feedback current caused by transitions on the common bus output when the enable signal E is at low potential and the device is in the high impedance third state.

Abstract: A field effect transistor (FET) structure suitable for MOS and CMOS IC fabrication processes includes spaced apart alternating source and drain regions distributed in a rectangular checkerboard pattern of horizontal and vertical rows. A first grid of intersecting horizontal and vertical conductive gate lines overlaps adjacent source and drain regions of the array and is dielectrically isolated from the source and drain regions by an insulating layer. The horizontal and vertical gate lines provide a single gate element distributed across the array which reduces FET channel length and channel resistance. A second grid comprising a set of parallel diagonal alternating source lead lines and drain lead lines is dielectrically isolated from the first grid. The source lead lines are electrically coupled to source regions and drain lead lines to drain regions.

Abstract: A lead wire bonding machine is described for ball bonding the end of a lead wire held in a bonding tool to a die pad of an integrated circuit chip and for wedge bonding a segment of the lead wire spaced from the ball bond to a lead frame finger during successive ball bond wedge bond cycles. The bonding machine includes a variable linear drive such as a solenoid or small linear motor coupled to the bonding head for applying the first bond force to the bonding tool during ball bonding and the second bond force to the bonding tool during wedge bonding. A control circuit coupled to the solenoid or other variable linear drive delivers a first current having a desired profile or amplitude wave envelope for applying the first bond force with a first force profile during ball bonding to die pads and by delivering a second current having a desired profile or amplitude wave form for applying the second bond force with a second force profile during wedge bonding to lead frame fingers.

Abstract: An improved lead wire ball bonding machine for bonding wire leads between an integrated circuit chip and the lead frame on which the chip is mounted is provided with a bonding tool position sensor coupled to receive the Z-motion velocity waveform signal to the servo motor which drives the bonding head and bonding tool. This sensor detects the signal level and direction of change or polarity of the Z-motion velocity waveform signal for determining the location of the bonding head and bonding tool. The bonding tool position sensor is coupled and adjusted for generating a first output signal corresponding to a first location of the bonding head and bonding tool during motion downward to the die pad of an integrated circuit chip prior to contact by the bonding tool and lead wire for ball bonding.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: A grid of electrical conductors for locating the position of a stylus utilizes a reduced number of line drivers. The grid utilizes twice as many conductors as required by conventional grids for a given resolution. The conductors are divided into coarse and fine sets which are interleaved and coextensive in the long dimension of the conductors. The coarse set is divided into subsets which consist of a predetermined number of conductors in close proximity to each other, adjacent coarse conductors being separated by only one fine conductor. The fine set is divided into a number of subsets equal to the number of conductors in each coarse subset. The number of conductors in each fine subset equals the number of coarse subsets. Each of the conductors of the fine subsets is spaced one from the other by a number of fine conductors equal to the number of coarse subsets. The conductors of each subset are connected to each other and to the output of a single driver.

Abstract: A method and circuits are described for sensing and detecting bond attempts and weld attempts during bonding and welding of lead wire. The method and circuitry are particularly applicable for detecting missed ball bonds and missed wedge bonds during bonding of lead wire between the die pad of a microcircuit chip and the lead frame on which the chip is mounted. A sensor (30) or sensing circuit (42) senses the different characteristic electrical condition of the lead wire (11) following a ball bond attempt and following a wedge bond attempt. A bond attempt indicator (45) indicates high resistance in the lead wire following a missed ball bond while weld attempt indicator (46) indicates low resistance in the lead wire (11) following a missed wedge bond. The lead wire (11) is isolated from uncontrolled contacts with ground potential while the lead wire is held in the bonding tool and bonding machine.

Abstract: A pencil device for a plotting machine comprises a housing (10) including a barrel (13) with a passage (13a) therethrough for receiving a lead (12) said passage having an exit for the lead at a forward end of said barrel; lead feeding means (11, 14, 15) located in said housing for containing spare leads and for continuously feeding the passage of said barrel with a lead; lead driving means (16, 17) for pressing the lead located in the passage against the recording medium during a writing operation; and means (36) for urging the forward end of the barrel in contact with the recording medium so that a consumed lead is replaced by a new lead without interrupting a trace being produced.

Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Abstract: A method for fabricating a semiconductor structure which reduces substrate current injection from lateral bipolar transistors. A buried layer of a first conductivity type is formed in a semiconductor substrate of opposite conductivity. An epitaxial layer of the first conductivity type is formed such that at least a portion of the epitaxial layer overlies the buried layer. Isolation oxide regions are formed in a epitaxial layer. The isolation oxide regions extend to the substrate to define an island of electrically isolated epitaxial material. A selected impurity of the first conductivity type is introduced into that portion of the epitaxial layer beneath the to-be-formed lateral transistor. The lateral transistor is formed in the epitaxial layer.

Abstract: Manufacture of bipolar substantially isoplanar integrated circuit structures is accomplished by rearrangement of the conventional masking steps and by the substitution and full integration of implanting methods for diffusion methods. A uniform nitride layer is deposited over the basic structure of epitaxial islands separated by isolation oxide regions thereby passivating and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from environmental contaminants. The nitride layer which forms part of a composite protective layer is maintained in place throughout a major portion of the fully integrated sequential implanting steps during which the collector sink, base and emitter regions are introduced into the epitaxial islands. At least a portion of the composite protective layer is a barrier to environmental contaminants throughout the process. The overall number of steps is reduced, etching steps minimized, and overall reliability of the structure improved.