Abstract: An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described.

Abstract: A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder array to eliminate the decoding of multiplier characters thereby reducing logic levels and enhancing performance. A means is illustrated for detecting single bit errors without redundancy or performance loss. While the array proper is more complex than other multibit algorithms, the multiplexers needed by those earlier systems are no longer required. The small increase in complexity of the array proper eliminates the need for decoding of the multiplier bits or other interaction between the multiplier groups. The net effect is a reduction in logic with faster operation because of the omission of the decoding requirement.

Abstract: A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A starting bit code defines the location of the start of the bit field to be written and a field length code defines the number of bits that are to be merged and written. The combination of the starting bit code and the field length code define the ending bit control for the bits to be written, and are further utilized to control word boundary crossing into the next sequentially addressed memory word when the bit field to be written cannot be completed in the addressed word.

Abstract: A flexible moulded plastic panel closure is provided with a plurality of latches and retainers to permit the flexible moulded plastic panel to be attached through an aperture in a rigid wall of a chassis of a video display terminal. The flexible moulded plastic panel is provided with a plurality of resilient retaining fingers and tolerance springs for precisely mounting and holding an axial flow electric fan in a predetermined position to provide circulated air cooling for heat producing electronic components mounted inside of said rigid chassis.

Abstract: A video display terminal (VDT) is provided with a controller having six digital logic lines capable of defining sixty-four different colors. An eight color color display monitor (CDM) having three red, green and blue (RGB) video input lines is connected to a pulse width modulation converter capable of converting the sixty-four digital input conditions on the six low level voltage logic lines to sixty-four different color control conditions on the three video input lines.

Abstract: A relatively short broad band monopole coaxial antenna is provided with a center conductor and an outer radiator. The antenna is mounted above a ground plane and comprises a bare outer radiator portion adjacent the ground plane and a portion remote from the ground plane which is covered with a variable thickness microwave absorbent material. The signal to be transmitted is applied to the base of the monopole antenna adjacent the ground plane. Non-radiated signals propagate up the antenna. The high frequency components are absorbed by the microwave absorbing material. A tip matching network and a base matching network are coupled between the outer conductor and the ground plane for attenuating and matching the low frequency components of the non-radiated signals. The resulting monopole coaxial antenna has no undesirable reflections and has the appearance of infinite effective length antenna.

Abstract: An accurate radio frequency ranging system is provided for measuring the time required for a signal to be transmitted from a ground station to a remote station and to be returned to the ground station. The ground station is provided with a master reference clock that is employed to drive a first pseudonoise generator. The ranging system in the ground station is started by a unique and predetermined start epoch signal produced by the first pseudonoise generator. The first pseudonoise generated signals are transmitted to the remote station where they are tracked and sensed. When the original start epoch signal is sensed at the remote station, it is employed as a trigger or read signal to initiate the generation of a stop epoch signal. The stop epoch signal is retransmitted to the ground station and stored in a register where it is compared with pseudonoise generated signals being retransmitted from the remote station to the ground station.

Abstract: The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped.

Abstract: A superconducting quantum interference device (SQUID) is direct current biased through physical connections asymmetric to, and preferably maximally asymmetric to, the two Josephson junctions. The asymmetric SQUID so created is, responsively to such physical asymmetry, biased for operation in the linear region of the input magnetic flux/output (voltage or current) device response curve. A resistance of specified value is connected in parallel, or shunt, to the parasitic bridge capacitance of the asymmetric SQUID in order to minimize hysteresis. Two asymmetric SQUIDS of opposite asymmetry are serially connected as a push-pull linear amplifier stage which exhibits zero output (voltage or current) at zero input magnetic flux, and which is specifiable in parameters of construction so as to exhibit optimum linearity of response about such point.

Abstract: A method of and apparatus for encoding computer program instructions and data greatly reduces the total storage requirements. Upon compiling each computer program segment, statistics are generated regarding the frequency of use of each unique program operator and each unique program operand. The operators and operands are encoded using the information theoretic encoding technique. A conversion table is also prepared which enables the object computer to translate the encoded operands and operators during that time when the computer program segment is being executed. Apparatus within the object computer decodes the encoded operands and operators using the conversion tables enabling execution of the computer program segment.

Abstract: A high speed data base search system which contains a general purpose computer coupled to a special purpose processor called the High Speed Search Function or HSSF. The HSSF may be external to the computer having a standard Input/Output communication path. An alternative approach places the HSSF internal to the computer providing communication via an internal bus. The HSSF is identical in either configuration except for the interface logic. The HSSF is programmable by the computer to perform complex searches on variable size data bases. The internal memory of the HSSF is loaded with the data base to be searched. Registers within the HSSF are loaded with reference words which define the search bounds. The field format register of the HSSF is loaded with a definition of the data base. The field comparison register is loaded to define the field-by-field search criteria. The Boolean Expression loaded into the HSSF defines which compare results are to be considered a hit.

Abstract: A method and apparatus for pseudorandomly decrementing the intensity of data that is displayed on a raster scan display screen. The apparatus essentially comprises means for selecting and partially decrementing data from an image memory and means for controlling the rate at which the partially decremented data is written back into the image memory so that an apparently uniform phosphor decay rate is observed by a viewer.

Abstract: A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, temperature, sensor via a second diode (system ground is a return). A multiplicity, nominally 16, of such single wire connected sensor pairs are selectable in accordance with an externally (microprocessor) furnished address. During a first time period, an externally (microprocessor) selected interrogation of temperature causes a first, positive, voltage bias to be applied to the selected sensor pair resulting in a current linear with temperature (over the range of 0.degree. C. to 100.degree. C.) in the second sensor. This current is transformed to voltage, offset by 273.degree. Kelvin, amplified, and converted to a digital value for issuance to an external (microprocessor) requestor.

Abstract: A cooling system monitoring assembly incorporating a heat generating element for simulating heat generation of components in the system, together with heat sensing element responsive to the heat generating element for providing temperature signals when the temperature of the heat generating element is sensed to have exceeded a predetermined threshold is described, thereby indicating the level of temperature fault. A support assembly is described for supporting the heat generating element in the heat transfer relationship to the monitored cooling system, while supporting the heat sensing element. A system for monitoring a plurality of subassemblies associated with the monitored cooling system and identifying the location of detected temperature fault condition is also described.

Abstract: A Drill Bit detector for use with numerically controlled drilling machine capable of sensing missing or broken Drill Bits in the range of 1 mil to 30 mils in diameter, or larger, is described. An infrared emitting diode is driven at a predetermined frequency with the pulsed light being directed through fiber optic cable directed at a portion of the Drill Bit to be detected. A change of light intensity occurring when a Drill Bit is missing is detected and the pulsed light detected converted to a pulsating electrical signal at the input frequency of the pulse light source. A frequency responsive circuit converts the pulsating electrical circuit to a digital signal indicative of the absence of the sensed Drill Bit. A timer determines whether or not the sensed digital signal occurs for a predetermined threshold time period, and causes it to be ignored as spurious if less than the predetermined time interval, or causes the drilling machine operation to be halted if occurring longer than the threshold time period.

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N.

Abstract: A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET. A second feedback loop created guard circuits on the cases of the input FET and the drain circuit regulator transistor, thereby mitigating junction to external circuitry capacitances. A third feedback loop modifies essentially constant current flow in the source circuit of the input FET in order to compensate for capacitance within that circuit. When utilized in compact form for microprobing of low voltage nanosecond rise time signals, the amplifier demonstrates an effective input capacitance of less than 0.5 picofarads.

Abstract: Direct current inrush upon connection of a capacitive load to a d.c. voltage is limited through an intermediary circuit. Within such circuit the inrush current is sensed by a series resistance and such sensing is utilized via a feedback loop, to control a series current regulating transistor to be cyclically conducting or non-conducting of a first direct current path. A second direct current path through freewheeling diodes flows current to the load only when such series current regulating transistor is non-conducting of such first path current. After fully charging the capacitive load, howsoever slowly as desired, the first current path conducts with low power dissipation while the second current path is non-conducting. The circuit is further controlled to be correctly operative for control of inrush current during the turn-on, or disruption of, fundamental power to such circuit.

Abstract: A data word of less than or equal to 2.sup.N bits is counted for the number of binary "1's" contained therein in log.sub.2 2.sup.N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data.