Patents Represented by Attorney Kenneth T. Grace
  • Patent number: 4424625
    Abstract: A removal tool for removing strip electrical connectors held in place by friction contact with electrical interconnection ends associated therewith is described. A pair of spaced apart wall members have inclined plane members associated therewith for engaging the undersurface of the connector to be removed for forcing the connector away from the support surface for sequentially disengaging the electrical interconnecting pins as the removal tool is moved axially along the longitudinal length of the connector.
    Type: Grant
    Filed: January 4, 1982
    Date of Patent: January 10, 1984
    Assignee: Sperry Corporation
    Inventor: Daniel L. Callahan
  • Patent number: 4419629
    Abstract: A switching circuit for automatically selecting one of a plurality of normally operable asynchronous oscillators is provided with a selection switch for selecting a new oscillator while the formerly selected oscillator is still producing an output. The switching circuit employs the output of the newly selected oscillator to disable the formerly selected oscillator and to subsequently enable the output of the newly selected oscillator to be coupled to the oscillator output of the switching circuit, thus, preventing switch-over from one oscillator to the other during a metastable period.
    Type: Grant
    Filed: June 25, 1980
    Date of Patent: December 6, 1983
    Assignee: Sperry Corporation
    Inventor: Steven M. O'Brien
  • Patent number: 4418393
    Abstract: Apparatus is provided for decreasing the acquisition time for recovering spread spectrum codes. The transmitted spread spectrum code is preceeded by a sync signal to establish system time at the receiver. The received coded data signals are applied to a matched filter or a delay line such as a surface acoustic wave device. The number of chips in the delay line is made an integral fraction of the number of chips in the word to be detected. The signals stored in the delay line are detected chip by chip as the coded data passes through the delay line. The resultant output analog signals from the delay line is digitized and stored chip by chip in a digital memory, such as a shift register, having the same chip storage capacity as the sequence group being transmitted. The values of chips in the digital storage memory are recirculated back to the input of an adder.
    Type: Grant
    Filed: October 27, 1980
    Date of Patent: November 29, 1983
    Assignee: Sperry Corporation
    Inventor: John W. Zscheile, Jr.
  • Patent number: 4418400
    Abstract: An improved magnetic memory system in which binary data are stored as cross-tie, Bloch-line pairs, which are serially propagated downstream along a cross-tie wall in a magnetizable layer by appropriate drive fields. The magnetizable layer is configured into a data track whose two opposing edges are formed into patterns of asymmetrically shaped edges which form successive narrow portions with wide portions therebetween, and which are formed about the geometric centerline of the data track. The improvement comprises forming a plurality of energy wells along the geometric centerline of the data track and, transverse to the geometric centerline of the data track in the areas of the narrow portions where the cross-ties are stored but not in the areas of the geometric centerline.
    Type: Grant
    Filed: December 22, 1980
    Date of Patent: November 29, 1983
    Assignee: Sperry Corporation
    Inventors: Gregory J. Cosimini, David S. Lo, Maynard C. Paul
  • Patent number: 4417249
    Abstract: Undesirable signals which are similar to desirable signals occur in transmitter-receiver systems, phased array antenna systems and null or steering antenna systems and are eliminated by a novel adaptive processor. The undesired signal is electronically cancelled by causing the weak undesired replica signal to track the stronger undesired reference signal. The circuitry structure employs a phase tracking loop which generates a phase tracking error signal. The phase tracking error signal is applied to a voltage controlled oscillator and a fixed delay element in the phase tracking loop path. The phase tracking loop is coupled to the weak signal path to shift the phase of the weak undesired replica signal so that it is in phase with the stronger undesired reference signal and may be electronically cancelled. The system may be employed to eliminate undesired signals and leave weak desired signals uneffected and easily detectable.
    Type: Grant
    Filed: September 8, 1980
    Date of Patent: November 22, 1983
    Assignee: Sperry Corporation
    Inventor: John W. Zscheile, Jr.
  • Patent number: 4416497
    Abstract: A strong U-channel shaped, spring clip of steel is used to retain by dual strong compressive clamping a strip conductor flexible flat ribbon cable at the edge of, and against a flat sheet substrate of epoxy or glass. Spring clamping is evenly uniformly exerted across all conductors across the width of the cable by finger-like spring segments integral with the clip. Stripped conductor ends of the ribbon cable are electrically connected to printed circuit lands upon the edge plane of the substrate by this clamping force. A second strong compressive force normal to the edge of the substrate is exerted by an elastomeric cellular silicone rubber pad at the base of the U-channel shaped spring clip which is held in strong compression when the spring clip is clamped upon the substrate. Assembly, disassembly, and reassembly are readily accomplished at zero sliding force or wear to connected conductors.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: November 22, 1983
    Assignee: Sperry Corporation
    Inventors: Gordon T. Brandsness, Robert L. Ebright, Alexander J. Orosz
  • Patent number: 4410963
    Abstract: An improved magnetic memory system in which binary data are stored as cross-tie, Bloch-line pairs, which are serially propagated downstream along a cross-tie wall and a magnetizable layer by appropriate drive fields. The magnetizable layer is configured into a data track whose two mirror-image, opposing edges are formed into patterns of asymmetrically shaped edges which form successive narrow portions, or necks, with wide portions therebetween, and which shaped edges are formed about the geometric central line of the data track. The cross-ties are structured in the data track by opposite-edge necks at which the ends of the cross-tie are magnetically stable.
    Type: Grant
    Filed: October 5, 1981
    Date of Patent: October 18, 1983
    Assignee: Sperry Corporation
    Inventors: David S. Lo, Maynard C. Paul, Lawrence G. Zierhut
  • Patent number: 4408191
    Abstract: A keyboard, having a plurality of actuatable key switches and an encoder responsive to actuation of each of the key switches for generating a character associated with each actuated key switch, includes a cycle time controller for making all of the characters potentially cycleable. The keyboard encoder, in addition to generating a character, will also generate a KEY SWITCH ACTUATED signal upon actuation of any one of the key switches and until the key switch is deactuated. The cycle timer controller responds to the generation of the KEY SWITCH ACTUATED signal and generates, after the lapse of a predetermined period of time from when the key switch was initially actuated and while the KEY SWITCH ACTUATED signal is still being generated, a CYCLE CHARACTER signal which may be used by a programmable terminal to cause cycling of the character generated by the decoder upon actuation of the key switch.
    Type: Grant
    Filed: December 24, 1981
    Date of Patent: October 4, 1983
    Assignee: Sperry Corporation
    Inventor: David M. Fowler, III
  • Patent number: 4398798
    Abstract: Disclosed is an apparatus for and a method of establishing the domain walls within a stripe-domain supporting magnetizable film in a radially directed orientation, the separation of which is proportional to the distance from the center of the diffraction grating. The apparatus includes means for coupling to the stripe-domain supporting magnetizable film an orienting field that is directed orthogonal to the plane of the film but whose intensity from the center of the field source is inversely proportional to the distance from the center of the field source and further including means for coupling to said film an AC tickle field of significant to decreasing to zero amplitude for overcoming the hysteresis of the film.
    Type: Grant
    Filed: December 18, 1980
    Date of Patent: August 16, 1983
    Assignee: Sperry Corporation
    Inventors: John A. Krawczak, Ernest J. Torok
  • Patent number: 4398269
    Abstract: Apparatus for preventing the writing of data into an MNOS memory during various time intervals, whereby the over-writing and premature fatiguing of the differential voltage separation of the memory cells is prevented. The apparatus comprising an access memory that flags each address when it is first written during a write protect interval so that upon subsequent attempts to write the same address a write abort will occur.
    Type: Grant
    Filed: July 23, 1981
    Date of Patent: August 9, 1983
    Assignee: Sperry Corporation
    Inventors: Raymond C. Hedin, Dennis L. Amundson
  • Patent number: 4397034
    Abstract: A system for transmitting desired information is provided which has a very low probability of being intercepted. The system combines a well known narrow bandwidth directional antenna for limiting the interception of the main beam information signal with a novel random noise generated signal which guarantees that the sidelobe signals which also contain the desired information cannot be distinguished as information signals.
    Type: Grant
    Filed: March 26, 1981
    Date of Patent: August 2, 1983
    Assignee: Sperry Corporation
    Inventors: Benjamin V. Cox, Billie M. Spencer, John W. Zscheile, Jr.
  • Patent number: 4393921
    Abstract: An electronic circuit controls a non-linear electromechanical valve in order that the temperature of approximately 25 gallons of coolant water within a reservoir may be maintained within +2.8.degree. C. to -0.0.degree. C. of a set point temperature from 35.degree. F. to 100.degree. F. The valve regulates circulation of such coolant within a secondary cooling loop incorporating a non-linear heat exchanger for thermal exchange with building water flowing from 20 to 30 gallons per minute. The reservoir coolant water is subject to an essentially instantaneously variable thermal load of 0 to 20 kilowatts due to circulation through logic modules in a primary coolant loop. The electromechanical valve control circuit receives an external set point temperature signal, and a reservoir coolant temperature signal which is offset in conversion from degrees Kelvin to degrees Centigrade.
    Type: Grant
    Filed: September 13, 1982
    Date of Patent: July 19, 1983
    Assignee: Sperry Corporation
    Inventor: Terry B. Zbinden
  • Patent number: 4394642
    Abstract: A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.
    Type: Grant
    Filed: September 21, 1981
    Date of Patent: July 19, 1983
    Assignee: Sperry Corporation
    Inventors: Robert J. Currie, Glen D. Rattlingourd, Billie M. Spencer, John W. Zscheile, Jr.
  • Patent number: 4393315
    Abstract: This invention provides a novel high-gain stabilized converter circuit which is adapted to convert emitter coupled logic (ECL) signals for use in gallium arsenide (Ga As) circuits. The novel converter is adapted to be made in gallium arsenide logic on the same chip as the logic circuitry which it is driving. The converter includes a novel differential amplifier having a level shifting network at the active input and a second level shifting network at the reference input to provide a stabilized high-gain circuit which is compensated for variations in temperature and process deviations.
    Type: Grant
    Filed: May 18, 1981
    Date of Patent: July 12, 1983
    Assignee: Sperry Corporation
    Inventors: Tedd K. Stickel, Stephen A. Ransom
  • Patent number: 4388136
    Abstract: A method of fabricating a "hybrid" multilayer printed circuit board combining two dissimilar plastic layers of polyimide resin/glass and of epoxy resin/glass laminates. The finished hybrid multilayer printed circuit board is for, e.g., the support of and electrical interconnection to a plurality of magnetizable memory cores. The method includes sandwiching a plurality of epoxy-glass printed circuit boards having the desired copper patterns on both sides between two polyimide-glass printed circuit boards, each having the desired copper pattern on only one side. All the printed circuit boards are laminated with epoxy-glass prepreg to form a single hybrid multilayer printed circuit board consisting of the sandwiched epoxy-glass printed circuit boards and the sandwiching polyimide-glass printed circuit boards. Interconnections between patterned layers are formed by copper-plate throughholes.
    Type: Grant
    Filed: September 26, 1980
    Date of Patent: June 14, 1983
    Assignee: Sperry Corporation
    Inventors: Jaken Y. Huie, Dan Jacobus
  • Patent number: 4386401
    Abstract: The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.
    Type: Grant
    Filed: July 28, 1980
    Date of Patent: May 31, 1983
    Assignee: Sperry Corporation
    Inventor: Steven M. O'Brien
  • Patent number: 4386349
    Abstract: A method and apparatus whereby an auxiliary yoke is used in conjunction with a CRT display to correctively deflect the electron beam to a true position within each pixel of a graphics figure, as the graphics figure is displayed on the CRT's screen. The apparatus thus increasing the display's resolution within each pixel so as to permit the smoothing of the displayed graphics figures.The improved resolution being achieved via a four bit binary position correction code, three bits of which are stored in the image memory at those memory addresses corresponding to the coordinates of the pixels that comprise the graphics figure, and one bit of which position correction code is stored at the immediately preceeding memory addresses. The entire position correction code in turn being decoded as the image memory is read and used to drive one or the other of the x and y coil pairs of the x-y auxiliary yoke.
    Type: Grant
    Filed: April 28, 1981
    Date of Patent: May 31, 1983
    Assignee: Sperry Corporation
    Inventors: Mauritz L. Granberg, David G. Hanson, Robert L. Rajala, William G. Whipple
  • Patent number: 4384325
    Abstract: Apparatus for and method of searching a data base using variable search criteria. The data base consists of a set of files or portions thereof. Each file is divided into a number of records whereby all records of a given file have the same format but the records of different files may have different formats. A field format register is used to define the format of the records within a given file. The field format register specifies the location and width of each field within a record. To perform a search, a field-by-field comparison of each record is made to a reference word. The comparison yields a less than, equal to or greater than result for each field of each record. A field comparison register describes the expected result of the field-by-field comparison. A given field is designated true if the comparison yields the expected result specified for that field in the field comparison register.
    Type: Grant
    Filed: June 23, 1980
    Date of Patent: May 17, 1983
    Assignee: Sperry Corporation
    Inventors: Leo J. Slechta, Jr., Bennett W. Manning, Nancy E. Preckshot, Howard M. Wagner
  • Patent number: 4382257
    Abstract: Any number N of light emitting diode (LED) push-button indicator-switches are connected by one wire each to a corresponding N interconnected assemblages of four cross-coupled logical elements each. A pushbutton activated signal input through a one connective wire causes a cross-coupled flip-flop storage action within the associated assemblage which will maintain the L.E.D. lit by outputting on the selfsame connective wire after the pushbutton is released. A one-shot circuit merged in each assemblage clears via the interconnect the stored signals of all other assemblages when a new pushbutton signal is activated. One of N selections between N indicator switches is thusly obtained with only one wire connection to each.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: May 3, 1983
    Assignee: Sperry Corporation
    Inventor: Joseph M. Cortner
  • Patent number: 4381550
    Abstract: Logic circuit hardware is provided for dividing a binary fraction divisor into a smaller binary fraction dividend to provide a binary fraction quotient.Initially, the divisor is stored in a storage register with its sign in the highest order bit position and remains unchanged during the division operation. Initially, the dividend is stored in a dividend shift register and is shifted left one bit before being applied to a parallel adder to perform a partial divide operation. A clock signal is provided to time the division operations, wherein, the stored dividend is added to the stored divisor in a parallel binary adder. When the highest order or sign bit of the adder is positive, the sum of the dividend and the divisor are stored in the dividend register and a binary one is stored in a quotient register. When the highest order or sign bit of the adder is negative, the dividend register is shifted left and a binary zero is filled in the quotient register.
    Type: Grant
    Filed: October 29, 1980
    Date of Patent: April 26, 1983
    Assignee: Sperry Corporation
    Inventor: Dan C. Baker