Abstract: A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate array assembly generally multiplying successive eight bit bytes of the multiplier two bits at a time in each of four ranks to the full width multiplicand and producing a partial sum and carry at the end of each cycle. Each partial sum and carry then being fedback, aligned and added into the partial sum and carry produced during the multiplication of the next successive multiplier byte, until the multiplication is complete and at which time the final partial carry is converted and added to the final partial product to produce the final product.

Abstract: A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control one or more system's accessibility to peripheral subsystem's from a central location. It is able to provide this control with the capability of either allowing a peripheral subsystem to be concurrently accessed by more than one system or forcibly ensuring that the peripheral subsystem is exclusively accessible by only a single system.

Abstract: A computer digital logic circuit utilizing an encoded Read Only Memory (ROM) and multiplexor elements is used to translate top-level shift control signals, such as arise from instruction translation, into the low-level control of selecting data input to, and controlling the shift count in, a shif matrix during a generalized computer shift operation. ROM size is held to only 64 addresses.times.16 bits per addressed cell in controlling selectable circular, selectable sign fill, single precision or double precision (dual pass) shifting in a sixteen bit shift matrix because the ROM is addressed with only part of the top-level shift control signals. Remaining top-level signals select among encoded outputs of the ROM in four multiplexor circuit elements to produce low-level gating control signals, called preselector control, which ultimately enable selection among two registers' data and sign fill data inputs to the shift matrix. The ROM directly produces the shift count control of the shift matrix.

Abstract: Apparatus for and method of providing a variable speed cycle time for synchronous machines. The synchronous machine performs a number of functions, wherein the execution time for a given function is dependent upon the input quantities. Timing for the input dependent function is divided into fixed and variable sequences. A synchronous counter is loaded with a quantity representative of the input quantities. The synchronous counter then controls the duration of the variable sequences based upon the representative quantity. Since it is clocked by the system clock, the synchronous counter controls the variable sequences synchronously with the controlling of the fixed sequences.

Abstract: An apparatus for distributing the control of data transfers within single instruction stream multiple data stream processors. Each of the parallel processors or arithmetic units is coupled to a dedicated local memory. A main memory provides storage of system data. Each dedicated local memory and the main memory are coupled to a bus interface unit. Each bus interface unit is coupled to a common data bus for the transfer of data between the main memory and the dedicated local memories. Each bus interface unit provides the control functions required to transfer data between the common data bus and the main or local memory to which it is coupled. One bus interface unit is designated the resource controller. The resource controller performs all of the functions of a bus interface unit and also provides the system level functions of supplying clock signals and performing bus arbitration.

Abstract: A method and apparatus for eliminating narrow band noise and interference from a wide band signal while maintaining the wide band signal substantially intact.

Abstract: Each of the exclusive OR (XOR, or odd parity) and exclusive NOR (XNOR, or even parity) logical functions as between two signals input in both normal and inverted form is generated from separate logic circuits of two transfer gates implemented in complementary metal oxide semiconductor (CMOS) very large scale integrated circuit (VLSIC) technology. Replications of paired such XOR and XNOR logical circuits within a parity tree allow parity generation/detection as between 2.sup.N signals input in both normal and inverted form in only N propagation stages of typically average 0.9 nanosecond delay each stage when implemented in 11/4 micron feature size CMOS VLSIC.

Abstract: A cyclical machine forming tool utilizes positionally justified form knives so that, nominally, a selected 80 out of 120 total stripped wire ends of flat ribbon cable may be selectively simultaneously formed, for bent, into a contour such as is useful for soldered attachement to printed circuit cards. Positional justification of wire-forming hammer elements called form knives, nominally 41 in number, across a variable distance, nominally 1.676.+-.0.009 inches, is expediently repetitively accurately accomplished by wedging them apart with interspersed counterposed knife elements, nominally 40 in number, called adjuster knives.

Abstract: A nondestructive readout, random access memory system is disclosed. The memory is formed of a plurality of discrete thin ferromagnetic film memory elements in which binary data are stored as the presence, or absence, of cross-tie, Bloch-line pairs. Column lines and row lines form a matrix array of the memory elements, one at each column line, row line intersection. Cross-tie, Bloch-line pairs are formed in the memory elements by the selective coincidence of row line and column line write drive fields while readout of the presence, or absence, of the cross-tie, Bloch-line pair is by a coincident row line read drive field and a column read current signal that flows through the memory elements aligned along a selected column. A read amplifier is differentially coupled across the one fully selected memory element to detect a first, or second, opposite polarity output signal that is indicative of the presence, or absence, of a cross-tie, Bloch-line pair at the one fully selected memory element.

Abstract: The invention provides internal self testing within an integrated circuit chip at all points along the logic chain. Internal stimulus generators and supervisory control circuits for the generators formed integrally within a VLSI chip are utilized together with integrally formed multiple fault detectors to provide self testing of the logic chain, mechanical interconnection failures, and power and clock pulse checking. The invention is utilizable in conjunction with either single or duplicate logic, which latter may be either duplicate complementary logic or duplicate functional logic. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. The invention eliminates the need for sophisticated ancillary test systems for diagnostic and go/no-go or confidence testing for hardware at the chip, board and system level.

Abstract: An automatic Memory Module sensing and Memory Module address assignment system during an initializing sequence is described. Each Memory Module has a memory assignment register associated therewith, and all memory assignment registers are initialized to an illegal Memory Module address. The interlock and switch signals are sequentially evaluated under control of a scan counter and decoder. A memory assignment counter is utilized to develop sequential Memory Module addresses and is advanced for each Memory Module found to exist in the system. The memory assignment register for the Memory Module under consideration is set to the address specified in the memory assignment counter if the Memory Module is determined to be present, or is left storing the illegal code if the Memory Module being considered is not present in the system or is switched off.

Abstract: A color cathode ray tube is provided in a color monitor of a video display terminal. The red, green and blue color video input lines are connected to novel control circuits which permit the selection of several different shades of colors for the background or cursor. The circuits which control the background colors are pulse modulated to provide digital shade control of the background color selected and automatically control the color of the cursor so that a contrasting color is provided.

Abstract: A method of fabricating a "hybrid" multilayer printed circuit board combining two dissimilar plastic layers of polyimide resin/glass and of epoxy resin/glass laminates. The finished hybrid multilayer printed circuit board is for, e.g., the support of and electrical interconnection to a plurality of magnetizable memory cores. The method includes sandwiching a plurality of epoxy-glass printed circuit boards having the desired copper patterns on both sides between two polyimide-glass printed circuit boards, each having the desired copper pattern on only one side. All the printed circuit boards are laminated with epoxy-glass prepreg to form a single hybrid multilayer printed circuit board consisting of the sandwiched epoxy-glass printed circuit boards and the sandwiching polyimide-glass printed circuit boards. Interconnections between patterned layers are formed by copper-plated through-holes.

Abstract: A non-coherent receiving system is provided with a novel triple-bit matched filter detector system which provides two outputs indicative of the data stream being detected. A preliminary or soft decision is made concerning the state of the bits in the data stream. One of the outputs provides a best estimate of state of the data bit being detected and the other output provides the second best estimate of the state of the data bits being detected. The incoming data stream is processed and modified as it is shifted through a plurality of shift registers in real time employing the data bits subsequently detected. A controller is provided to make a plurality of predetermined evaluations of the state of the bits in the data stream and to provide a final or hard decision of the correct state of the data bits previously detected.

Abstract: A system and method for protecting electrostatic sensitive devices from damage caused by electrostatic discharge therethrough when being placed in electrical interconnection in an operating system is described. Electrostatic sensitive devices are mounted on a printed circuit carrier and have all ground circuits electrically connected to a common juncture. A guide block for cooperating with a guide pin during insertion is mounted on the printed circuit assembly. All guide pins are electrically coupled in common to a discharge potential. A spring contact is mounted in the guide block and electrically coupled to the common juncture, and is arranged for making contact with the guide pin prior to electrical contact of any signal pins with any connector terminals, whereby static charge is discharged through the discharge path without causing damage to the electrostatic sensitive device.

Abstract: An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture.

Abstract: An apparatus for and a method of correcting chromatic aberration in a multiwavelength input light beam deflection system incorporating a magneto-optic diffraction grating is disclosed. The diffraction grating generates a chromatic aberration induced plurality of first order light beams from the multiwavelength input light beam, each different wavelength light beam being deflected a correspondingly different angle .lambda. by the diffraction grating. Correction plates, designed to provide zero chromatic correction for a wavelength .lambda..sub.o with corresponding positive and negative chromatic correction for wavelengths about the wavelength .lambda..sub.

Abstract: In a digital data acquisition system, there is provided a coherent direct sequence spread spectrum receiving system. The coherent receiving system comprises an independent carrier tracking loop and three independent branches for detecting and locking on to a received psuedonoise data signal. The psuedonoise data signal being transmitted is provided with a time slot or discrete time portion during which no data is modulated onto the carrier. The carrier signal which is not phase modulated with digital data is tracked by the tracking loop so that the absolute phase of the carrier is never lost. The psuedonoise data signals are now recoverable in a coherent direct sequence spread spectrum receiver without the requirement of absolute phase determination or non-coherent detection.

Abstract: A ranging apparatus is provided having an encoded waveform signal which is generated by completely random sequence generator without second order statistics so that the waveform signal has a remote statistical probability of being analyzed. The modulated radio frequency waveform is transmitted to an object and the reflected signal is received by the ranging apparatus which comprises a digital solid state read-write memory arranged to have information written into the memory at a fixed frequency and arranged to have the information read out of the solid state read-write memory at a variable frequency to provide the equivalent of a rotating memory. The digital logic employed in the ranging apparatus is extremely accurate and not subject to drift and changes which could occur in analog type systems. The implementation of the ranging apparatus is accomplished with economical commercially available components thus providing an improved digital ranging apparatus.

Abstract: A portable electric hot air rework tool for directing a stream of turbulent hot air through removable and replaceable nozzles with a selectably sized orifice to predetermined size localized areas of a printed circuit assembly until a temperature sufficient to melt solder is achieved, thereby facilitating the soldering/desoldering of circuit components or parts of components mounted thereon. The apparatus essentially comprises a portable work station having upper and lower heat tubes, or plenums, through which a blower-forced stream of air made turbulent by turbulators with contra-pitched blades is directed, an adjustable support grid for supporting the pc assembly, within the directed air stream and a three-position switch for controlling the temperature and flow of the air in the heat tubes. An alignment positional indicator aids in precise location of the printed circuit assembly.