Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: A ball-grid array (BGA) semiconductor package (10,60,90) includes a substrate (31,61,91) attached to a support substrate (32,62 92). The substrate (31,61,91) has an opening (33) extending from an upper surface to a lower surface. An integrated circuit chip (18) is attached to the support substrate (32,62,92) within the opening (33). Bond pads (22) on the integrated circuit chip (18) are electrically connected to ball pads (42,73,106,108) on the lower surface of the substrate (31,61,91). Conductive solder balls (26) are attached to the ball pads (42,73,106,108). The support substrate (32,62,92) provides a low profile and functions as a standoff that limits the collapse of the conductive solder balls (26) when the BGA semiconductor package (10,60,90) is attached to an application board (46).

Abstract: A method for use with semiconductor devices (47) that have leads (49) electroplated with a solderable metal (53) includes exposing the solderable metal (53) to an elevated temperature sufficient to flow or melt the solderable metal (53). In a preferred embodiment, the solderable metal (53) is exposed to the elevated temperature before the leads (49) are severed from the leadframe (48).

Abstract: A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).

Abstract: An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions supplied by the instruction source into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received, at the rate required by the single instruction multiple data array processor, and as many times as required by the loop count field.

Abstract: A flow sensor device including a body portion that provides a pressure differential when placed in fluid stream and a pressure sensor portion associated with the body portion to sense the pressure differential. In one embodiment, the body portion (13,72,113) includes a channel (16,76,116) that extends from an entrance side (24,44,124) to an exit side (26, 46). The channel (16, 76,116) has an inner portion (27, 47,87) between the entrance side (24, 44,124) and the exit side (26, 46). The channel (16,76,116) has a first cross-sectional area at the entrance side (24,44,124) and a second cross-sectional area at the inner portion (27,47,87), which is less than the first cross-sectional area. The pressure sensor portion (14,74,114) includes a diaphragm (18,38,78,118) and is associated with the body portion (13,72,113) such that when a fluid passes through the channel (16, 76,116), a pressure differential is sensed by the pressure sensor portion (14,74,114).

Abstract: A method for selectively forming semiconductor regions (28) is provided, by exposing a patterned substrate (21) having exposed regions of semiconductor material (26,27) and exposed regions of oxide (24) to a first temperature and a semiconductor source-gas and hydrogen in an atmosphere substantially absent halogens, a blanket semiconductor layer (28,29) forms over the exposed regions of semiconductor material (26,27) and oxide (24). By further exposing the patterned substrate (21) to a second temperature higher than the first temperature in a hydrogen atmosphere, polycrystalline semiconductor material (29) formed over the exposed oxide regions (24) is selectively removed leaving that portion of the blanket semiconductor layer (28) over the exposed regions of semiconductor material (26,27). The method is suitable for forming isolated regions of semiconductor material for fabricating semiconductor devices and is not load dependent.

Abstract: An environmental sensor integrated with high current drive device is provided. An environmental sensor is fabricated on a semiconductor substrate using conventional MOS process used for N-well CMOS logic and DMOS power transistors. An N-well is preferably used as a junction etch stop for micromachining of mechanical sensor components. A high voltage P-type region is used to electrically isolate the high current device from the sensor device. By locating the sensor device away from the high current drive device on a common semiconductor substrate, good performance can be achieved from the sensor even while the high current device dissipates a large amount of power.

Abstract: A method of growing semiconductor crystals including inserting a single crystal seed (14) of a semiconductor material into a melt (12) and pulling the seed (14) at a first rate to gradually grow an elongated, single crystal first neck (15), altering the pulling rate to a second rate, slower than the first rate, to grow a shoulder (17) on the first neck (15) with a diameter greater than the first neck (15), continuing to pull at the second rate to form a second neck (18) with a diameter equal to the diameter of the shoulder (17), and altering the pulling rate to a third rate, slower than the second rate, to grow a single crystal elongated body (20) of the semiconductor material.

Abstract: An apparatus for probing high frequency electronic devices in wafer form includes a high frequency wafer probe (16, 56) having a conductor (36, 61), a dielectric layer (37, 71, 72), a grounding layer (38, 81, 82, 91), a signal probe needle (39,86), and a pair of ground needles (43, 72, 76) coupled to a substrate (11, 51). A plurality of high frequency wafer probes (16, 56) can be coupled to the substrate (11, 51) to probe high density high frequency electronic devices and to probe high frequency electronic devices having varying bonding pad layouts. The high frequency wafer probe (16, 56) is less sensitive to varying bonding pad height. The apparatus is suitable for probing high frequency electronic devices in a wafer manufacturing environment.

Abstract: A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.

Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: A method for manufacturing a liquid-containing microelectronic device package. The method includes steps of providing (32) a base (16) including a microelectronic device (22) and a seal area disposed peripherally about the base (16), providing (34) a lid (12) and providing (34) a sealant (14) disposed between the base (16) and lid (12). The method also includes steps of immersing (36) the base (16), sealant (14) and lid (12) in a liquid (24) having a temperature above a sealant activation temperature and maintaining (38) the base (16), sealant (14) and lid (12) in the liquid (24) for a time sufficient to allow the liquid (24) to enter between the base (16) and lid (12) and to heat and thereby activate the sealant (14). The method further includes removing (40) the base (16), lid (12) and sealant (14) from the liquid (24) to provide a sealed, liquid-containing microelectronic device package (10).

Abstract: A method for making a stable low threshold voltage p-channel power MOSFET device having a p-type gate layer (14) includes incorporating a p-type dopant into the gate layer (14) formed over a gate oxide layer (13). The p-type dopant is incorporated within the gate layer (14) under conditions that minimize diffusion of p-type dopant through the gate oxide layer (13) into the channel regions (31, 32). The process reduces the number of process steps necessary to manufacture a power MOSFET device.

Abstract: A IV-IV semiconductor device having a narrowed bandgap characteristic compared to silicon and method is provided. By incorporating carbon into silicon at a substitutional concentration of between 0.5% and 1.1%, a semiconductor device having a narrowed bandgap compared to silicon and good crystalline quality is achieved. The semiconductor device is suitable for semiconductor heterojunction devices that use narrowed bandgap regions.

Abstract: A method for manufacturing a liquid-containing microelectronic device package. The method includes steps of providing (32) a base (16) including a microelectronic device (22) and a seal area disposed peripherally about the base (16), providing (34) a lid (12) and providing (34) a sealant (14) disposed between the base (16) and lid (12). The method also includes steps of immersing (36) the base (16), sealant (14) and lid (12) in a liquid (24) having a temperature above a sealant activation temperature and maintaining (38) the base (16), sealant (14) and lid (12) in the liquid (24) for a time sufficient to allow the liquid (24) to enter between the base (16) and lid (12) and to heat and thereby activate the sealant (14). The method further includes removing (40) the base (16), lid (12) and sealant (14) from the liquid (24) to provide a sealed, liquid-containing microelectronic device package (10).

Abstract: A method for forming a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. By patterning the high temperature metal nitride layer (16) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal nitride layer (16) and a dielectric layer (17, 27) subsequently formed over the high temperature metal nitride layer (16) is significantly improved. The dielectric layer (17, 27) will adhere to the high temperature metal nitride layer (16) in high temperature environments. In addition, a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. The structure is suitable for power, logic, and high frequency integrated circuit devices.

Abstract: A method for forming a dielectric layer (16) on a high temperature metal layer (14) is provided. By processing the high temperature metal layer (14) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal layer (14) and a dielectric layer (16) subsequently formed on the high temperature metal layer (14) is significantly improved. The dielectric layer (16) will adhere to the high temperature metal layer (14) in high temperature environments. The method is suitable for forming multi-layer metallization and buried layer structures for semiconductor integrated circuits.

Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.