Abstract: A fabrication process and integrated circuit formed thereby are provided in which relatively thin sidewall spacers extend laterally from opposed sidewall surfaces of a transistor gate conductor. The present invention contemplates forming a gate structure upon a semiconductor substrate. Lightly doped drain impurity areas may be formed in the semiconductor substrate aligned with sidewall of the gate structure. An oxygen-containing dielectric layer is deposited upon the semiconductor topography, followed by deposition of an oxidizable metal upon the dielectric layer. The oxygen-containing dielectric and the oxidizable metal are thermally annealed such that metal oxide spacers are formed adjacent sidewall surfaces of the gate structure. In an embodiment, portions of the dielectric and the metal are selectively removed prior to the anneal. In an alternate embodiment, the metal and the dielectric are annealed first, followed by selective removal of portions of the resulting metal oxide.

Abstract: A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate.

Abstract: A transistor and transistor fabrication method are presented wherein ultra small spacers are formed adjacent sidewall surfaces of a gate conductor. A first dielectric material is deposited over a semiconductor topography. The first dielectric is partially removed to expose a portion of the gate conductor, and a second dielectric material is deposited upon the first dielectric material and the gate conductor. The second dielectric material is anisotropically etched such that the second dielectric material is preferentially removed from substantially horizontal surfaces and retained adjacent substantially vertical surfaces. The first dielectric material is then selectively removed from areas not masked by the second dielectric material. The composite spacers thus formed adjacent sidewall surfaces of the gate conductor are thinner than spacers formed using conventional techniques. Sub-0.

Abstract: A semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls on the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate includes a first and a second sidewall. Exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement.

Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.

Abstract: A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a series of laterally spaced surfaces to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. The multilayer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The polysilicon spacer is formed by an anisotropic etch, and the pre-existing etch stop prevents the anisotropic etch from damaging the source/drain and gate conductor regions beneath the etch stop. Further, the etch stop allows removal of the overlying oxide as well as the entire polysilicon during times when the multi-layer spacer is entirely removed. Removal of the various layers does not damage the underlying substrate due to the presence of the etch stop.

Abstract: A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA). The microcontroller includes an execution unit, a DMA unit, one or more ASPs, and at least one input/output (I/O) pad formed upon a single monolithic semiconductor substrate. The execution unit is configured to execute instructions, preferably .times.86 instructions. Each ASP is configurable to generate an internal DMA request signal, which effectuates a DMA transfer of serial communication data, and multiple DMA control signals. Each I/O pad is adapted to receive an external DMA request signal generated by a device external to the microcontroller. The DMA unit includes selection logic coupled to one or more DMA channel circuits. The selection logic receives the internal and external DMA request signals as well as the DMA control signals, and produces a DMA request signal for each DMA channel circuit.

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted into regions of the active areas in close proximity to the trench isolation structure.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.

Abstract: A method is provided for forming a non-volatile memory cell in which the upper surface of the floating gate is polished to reduce surface irregularities, providing for the formation of a gate dielectric having a relatively high breakdown voltage thereon. According to an embodiment, a first gate dielectric is thermally grown upon a semiconductor substrate which later serves as the tunnel dielectric in the ensuing memory cell. A floating gate polysilicon is deposited across the first gate dielectric, followed by ion implantation of dopants and nitrogen therein. The upper surface of the floating gate polysilicon is then polished using, e.g., CMP. A second gate dielectric comprising high quality oxynitride may then be thermally grown across the polished surface of the floating gate polysilicon. Alternately, a ceramic having a relatively high dielectric constant may be formed across the floating gate polysilicon to serve as the second gate dielectric.

Abstract: A process for fabricating a semiconductor transistor in which a semiconductor substrate is provided and a gate dielectric layer formed on an upper surface of the semiconductor substrate. A base conductive layer is then deposited on an upper surface of the gate dielectric layer. The base conductive layer is patterned to form base sections of a first and a second gate structure. Source/drain impurity distributions are introduced into the semiconductor substrate using the base sections as a mask to form source/drain structures within the semiconductor substrate. An insulating support layer is then formed on a topography defined by the semiconductor substrate and the base section. The insulating support layer is planarized until an upper surface of the insulating support layer is substantially planar with upper surfaces of the base sections. A second conductive layer is then deposited. The second conductive layer includes gate portions and interconnect portions.

Abstract: Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions.

Abstract: A process is provided for forming to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate.

Abstract: A method of manufacturing a silicon substrate which optimizes extrinsic gettering during semiconductor fabrication is provided in which phosphorous ions are diffused into the backside surface of a silicon substrate during wafer slice manufacture. Forming gettering sites at the backside surface prior to gate polysilicon deposition, extrinsic gettering is optimized. Initially, both the frontside and backside surfaces of a silicon substrate are subjected to dopant materials. Thereafter, at least one thin film is formed on both the frontside and backside surfaces. The thin films are then removed from the frontside surface along with a layer of the silicon substrate immediately below the frontside surface to a depth of about 10.0 .mu.m. The final polishing step of a typical silicon wafer manufacturing process removes a layer of silicon to a depth of about 10.0 .mu.

Abstract: An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly sized spacers. The spacers can be made larger in lateral areas on transistors designated as lower performing transistors than smaller spacers used on transistors which are higher performing. The dissimilarly sized spacers produce correspondingly sized lightly doped drain (LDD) areas. Accordingly, the present integrated circuit includes on a single monolithic substrate both high and low performance transistors based upon formation of dissimilarly sized spacers at sidewall surfaces of select transistor gate conductors.

Abstract: The present invention advantageously provides a method for forming a transistor having decreased source-side parasitic resistance and an improved shallow junction, thereby providing for enhanced transistor performance and improved resistance to short-channel effects. Barrier atoms are selectively implanted into the semiconductor substrate prior to formation of lightly doped drains and source/drain regions. Barrier atoms present in the channel region under the gate structure prevent migration of the lightly doped drain implant impurities into the channel region, thus reducing parasitic resistance. Barrier atoms implanted into the junction region prevent migration of source implant impurities more deeply into the junction region, thus preserving the shallow junction.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.