Abstract: An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer.

Abstract: A method and apparatus for cleaning apertures within an input manifold of a semiconductor fabrication deposition tool is presented. Vapor phase chemicals that contain the required constituents are introduced into the tool through the input manifold. The apertures of the input manifold direct the gas flow towards the surface of the wafer where they are absorbed and react to form thin films. Film accumulates on the wafers but also in other places inside the chamber of the reactor. Those places include the sidewall surfaces of the gas delivery apertures. Apertures deposits can source contaminants thereby causing defects on the wafers. The presented cleaning mechanism is operably sealed to the input manifold on one end and to a vacuum pump at the other end. The vacuum cleaner comprises a rotating plate with a radial slot. Air flows from the input manifold, through the apertures, through the slot, and to the vacuum pump.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, the first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure.

Abstract: A heat transfer apparatus is presented accommodating elevational disparity of an upper surface of a semiconductor device with respect to the component side of a PCB without adversely affecting system reliability. The heat transfer apparatus includes a thermally conductive cap structure positioned between the semiconductor device and an ambient and thermally coupled to the semiconductor device. One embodiment includes one or more spacers which maintain a space between the cap structure and the semiconductor device. A chip mounted to the substrate of a ceramic BGA package is mechanically isolated from the cap structure by the spacers, preventing chip damage due to shock and vibration. A backing plate on a side of the PCB opposite the semiconductor device provides PCB structural support and additional heat transfer. Several fasteners attach the backing plate to the cap structure.

Abstract: A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth.

Abstract: An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

Abstract: A method for protecting the trench dielectric fill for a shallow trench isolation structure by forming a protective layer upon the upper surface of the trench dielectric is presented. In a preferred embodiment, the protective layer comprises a layer of nitride formed upon a layer of oxide. Various etch and cleaning processes during the semiconductor device formation may cause damage to the trench dielectric. A shallow trench is typically formed early in the process sequence. A trench dielectric is deposited into the shallow trench and then planarized so that the upper surface of the trench dielectric is at the same level as the upper surface of the trench dielectric.

Abstract: The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location.

Abstract: A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures.

Abstract: An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral length of the gate conductor is reduced by forming a masking layer upon the gate conductor such that only a portion of the gate conductor is covered by the masking layer. The unmasked portion of the gate conductor is then removed to reduce the lateral length of the gate conductor. In this manner, a gate conductor having a lateral length that is significantly less than a lateral length attainable using a photolithographic process may be obtained.

Abstract: The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them.

Abstract: A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C.

Abstract: A system and method for using real mode BIOS calls to load an executable program for execution on a dedicated I/O processor before device drivers which communicate with the I/O processor have been loaded by an operating system. In the preferred embodiment, the system comprises a plurality of x86 processors coupled to a system memory. One of the x86 processors is designated as a dedicated I/O processor. A storage device stores an operating system for execution on the remaining processors, an executable program for executing on the dedicated I/O processor, such as a real-time kernel, and a device driver which is operable to execute on the remaining processors and to communicate with the real-time kernel executing on the I/O processor to perform I/o operations on an I/O device. The storage device also stores a loader program which is loaded by the operating system executing on a first of the remaining processors early in the process of booting the operating system.

Abstract: The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance.

Abstract: A low-profile heat transfer apparatus is presented for a surface-mounted semiconductor device employing a ball grid array (BGA) device package having a chip mounted upon a substantially flat upper surface of a substrate. The semiconductor device is mounted upon a component side of a printed circuit board (PCB), and the heat transfer apparatus is used to transfer heat energy from the semiconductor device to an ambient. A thermally conductive cap structure is positioned between the semiconductor device and the ambient. The cap structure includes a bottom surface having a first cavity sized to receive the substrate and possibly any decoupling capacitors. During use, the substrate resides within the first cavity. In a first embodiment, the chip resides within a second cavity in an upper wall of the first cavity during use. The chip and substrate are thermally coupled to the cap structure by a first and second thermal interface layer, respectively.

Abstract: An integrated circuit fabrication process is provided for forming silicon dioxide in the vacancies of a gate dielectric comprising metal oxide. The gate dielectric has a relatively high dielectric constant to promote high capacitive coupling between two conductive layers separated by the gate dielectric. The gate dielectric may be used in, e.g., a MOS transistor device or an EEPROM memory cell. The silicon dioxide is formed within the gate dielectric by first incorporating silicon atoms within the gate dielectric using gas cluster ion beam implantation. Gas cluster ion beam implantation affords shallow implantation of the silicon atoms. The gate dielectric is then annealed in a diffusion furnace while being exposed to a steam- or oxygen-bearing ambient. As a result of being heated, Si atoms react with O atoms to form SiO.sub.2 which fills oxygen vacancies in the gate dielectric. Absent the oxygen vacancies, the gate dielectric is less likely to allow current to leak between the two conductive layers. The SiO.

Abstract: The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant).

Abstract: An electrode reshaping process and apparatus is provided for use in a semiconductor etching device. A wafer is place between upper and lower electrodes of the semiconductor etching device. The apparatus and method selectively adjusts the shape of an upper electrode in the semiconductor etching device to compensate for non-uniformities inherent in the etching device. One or more motors attached to the upper electrode provide the electrode shaping forces in accordance with information provided by etch rate variation models stored in a host computer. With the shape of the upper electrode adjusted, the wafer can be etched more uniformally.