Abstract: A measurement system is presented for detecting the presence of one or more harmful chemical species within one or more chambers of a semiconductor wafer processing device. Chemical species of interest include oxygen (O.sub.2), nitrogen (N.sub.2), moisture (H.sub.2 O), and organic compounds associated with photoresist processing. Such organic compounds include isopropyl alcohol (CH.sub.3 CH(OH)CH.sub.3), acetone (CH.sub.3 COCH.sub.3), and ethyl-3-ethoxy propionate (C.sub.7 H.sub.14 O.sub.3). Candidate semiconductor wafer processing devices include evaporation, sputtering, and low pressure chemical vapor deposition (LPCVD) devices.

Abstract: An integrated circuit fabrication process is provided for forming relatively thin sidewall spacers extending laterally from upper portions of opposed sidewall surfaces of a transistor gate conductor which resides partially within a trench of a semiconductor substrate. The present invention contemplates etching a trench through a masking layer and partially through a silicon-based substrate arranged underneath the masking layer. A gate dielectric is then formed upon silicon-based surfaces which border the trench. A conformal dielectric layer is deposited across the masking layer and the gate dielectric, followed by the deposition of a gate conductor material across the dielectric layer. The gate conductor material and the dielectric layer are removed from above the upper surface of the masking layer. Portions of the dielectric layer interposed between the masking layer and the gate conductor are etched to a level commensurate with the substrate surface.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors.

Abstract: A method and apparatus capable of generating and executing large numbers of functional tests for complex digital electronic systems at low cost are presented. The apparatus includes a test generator which uses a decision tree representation of a verification space, derived from a functional specification of the digital electronic system, to generate functional tests. A decision tree representation of a verification space includes an initial goal node, a leaf goal node, and at least one intermediate goal node interconnected by a plurality of directed decision arcs formed between the initial goal node and the leaf goal node. Goal plans assigned to goal nodes include operations which generate functional tests. Functional tests are generated by recursively "walking" the decision tree, the choices of which goal node to visit next being made at random and according to decision weights assigned to each goal node.

Abstract: A manufacturing process in which semiconductor transistors are fabricated using a fluorine or nitrogen implant into the n-channel regions and an amorphization implant to beneficially limit the spreading of the source/drain impurity distributions thereby decreasing the junction depth and increasing the sheet resistance of the source/drain regions. Broadly speaking, a gate dielectric layer is formed on a semiconductor substrate. First and second conductive gate structures are then formed on an upper surface of the gate dielectric layer. The first conductive gate is positioned over the p-well region while the second conductive gate is positioned over the n-well region. An n-channel mask is then formed on the substrate and a first impurity distribution is introduced into the p-well regions. The first impurity distribution preferably includes a species of fluorine or nitrogen. A n-type impurity distribution is then introduced into the p-well regions of the semiconductor substrate.

Abstract: A driver circuit is presented which can transition between output voltage levels at a high switching speed. The preferred output driver is a PECL driver having both a correction circuit portion and a drive circuit portion. The correction circuit senses changes in the base-to-emitter forward bias voltage V.sub.BE of drive transistors within the drive circuit. Thus, any change in performance of those drive transistors is replicated in the correction circuit, which then produces a compensating current. The compensating current is modulated by a reference voltage value, and mirrored to the drive circuit. The drive circuit includes not only differential input transistors and differential drive transistors, but also a resistor coupled to the base terminal of each drive transistor. The resistor receives the compensating current which then offsets any change in voltage level (V.sub.OH or V.sub.OL) produced at the output of the drive transistors.

Abstract: An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned.

Abstract: A D/A converter for converting a given digital signal into an analog signal includes a plurality of capacitors (C1, C2 . . . , Ci) for storing an electric charge corresponding to a predetermined reference voltage (Vr+or Vr-). The reference voltage is selected depending on the digital signal during a period when a clock .phi.1 is at a high level. A switch selection (SUG1-SUGi, SB) is used to connect each of the plurality of capacitors between an input terminal and an output terminal of an operational amplifier 100 during a period when a clock +2 is at a high level.

Abstract: Broadly speaking, the present invention contemplates a semiconductor manufacturing process in which LDD regions of a semiconductor transistor are implanted after the heavily doped regions without requiring the removal of spacer structures from the sidewalls of the transistor gate. A semiconductor substrate is provided. The semiconductor substrate includes a channel region laterally displaced between first and second lightly doped regions. The first and second lightly doped regions are laterally displaced between first and second heavily doped regions of the semiconductor substrate. A gate dielectric is formed on an upper surface of the semiconductor substrate. A conductive gate structure is then formed on the gate dielectric. The conductive gate structure is aligned over the channel region of the semiconductor substrate. First and second spacer structures are then formed on first and second sidewalls of the conductive gate.

Abstract: A method for calibrating an optical pyrometer to an external reference point. By changing the focus of the optical pyrometer without physically moving the pyrometer, calibration of the optical pyrometer can be accomplished without modifying the semiconductor operation. Broadly speaking, the present invention contemplates an apparatus for calibrating an optical pyrometer. The apparatus includes a first optical source in a heating chamber with an optical port, an optical pyrometer, a mirror, and a second optical source. The optical pyrometer is positioned to receive light rays from a first optical source residing inside the heating chamber. The second optical source is located external to the heating chamber. The second optical source serves as an external reference point. The external location of the second optical source allows for calibration of the optical pyrometer without modification of the heating chamber or the first optical source residing inside the heating chamber.

Abstract: A method if provided for forming a diamond etch stop layer across a transistor to protect the source and drain junctions and the gate conductor of the transistor from being etched. The diamond may be CVD deposited from a hydrocarbon-bearing gas across the transistor. An interlevel dielectric comprising oxide is formed across the diamond etch stop layer. Contact openings may be etched through the oxide interlevel dielectric to the source and drain junctions and the gate conductor using a fluorine-bearing plasma. Advantageously, a high etch rate selectivity of oxide to diamond may be achieved using the fluorine-bearing plasma. As such, the plasma etch may be terminated well before significant portions of the diamond can be removed. Ti atoms may be implanted into regions of the diamond exposed by the contact openings and subsequently heated to render those regions of the diamond conductive.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.

Abstract: A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide.

Abstract: The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners.

Abstract: A method of doping a semiconductor substrate with a single masking step. A semiconductor substrate having a first region and a laterally displaced second region is provided. A patterned masking layer is then formed on an upper surface of the semiconductor substrate over the first region. A first well impurity distribution is then formed in the semiconductor substrate such that a peak concentration of the first well impurity distribution is located at a first well depth below the upper surface in the first region of the semiconductor substrate. The peak concentration of the first well impurity distribution within the second region of the semiconductor substrate is located at a depth approximately equal to the first well depth plus a well displacement. A second well impurity distribution is then formed in the semiconductor substrate. A peak concentration of the second well impurity distribution within the second region of the semiconductor substrate is located at a second well depth below the upper surface.

Abstract: A method is presented for consistently forming low resistance contact structures in vias between interconnects. A two-step adhesion layer deposition process with an intermediate particle removing step is employed to ensure sidewalls and bottom surfaces of vias are adequately covered with adhesion layer material prior to via plug formation. Two separate layers of an adhesion layer material (e.g., TiN) are deposited, each layer having a thickness which is adequate for that layer to act as a nucleating surface for subsequently deposited via plug material (e.g., W). The particle removing step is performed following deposition of a first adhesion layer. During the particle removing step, particles of the adhesion layer material are removed from the upper surface of the first adhesion layer, including particles blocking via openings.

Abstract: An improved planarization process for a trench dielectric is presented. A shallow trench isolation structure is formed into the semiconductor substrate. A thin oxide layer is grown upon the trench floor and upon the trench sidewalls, and then a trench dielectric, preferably TEOS deposited using a chemical-vapor deposition CVD process, is deposited into the trench dielectric and upon the semiconductor substrate. The upper surface of the trench dielectric conforms to the underlying contour defined by the shallow trench and the semiconductor substrate. Subsequent device formation requires a substantially planar semiconductor. Conventionally, a combination of masking and etching are used, prior to chemical-mechanical polishing ("CMP"), to aid the planarization process. The extra steps add cost and unnecessary complexity to the process. An alternative planarization process is proposed which uses hydrogen silsequioxane-based flowable oxide ("HSQ").

Abstract: A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and a pad oxide layer is deposited on the semiconductor substrate. A barrier layer is then deposited on the pad oxide layer and a photoresist layer is formed over the barrier layer and patterned to form a photoresist mask. The photoresist mask is aligned over active regions of the semiconductor substrate. An oxygen bearing species is then introduced to an isolation region of the semiconductor substrate. The isolation region is laterally displaced between the active regions. The introducing of the oxygen bearing species into the isolation region results in the formation of an oxygenated region of the semiconductor substrate.

Abstract: The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, .alpha. alumina, .gamma. alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution including either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed.

Abstract: A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.