Abstract: A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory cell may have a magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously reduce and/or eliminate the effects of variations in the fabrication process. In addition, an asymmetrical memory shape may induce a relatively consistent equilibrium vector state, allowing a single switching mechanism to set the magnetic direction of the cell. Furthermore, a method is provided for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

Abstract: In a system, method and program for identifying information accessible over a client/server network, search results obtained by a search engine running on a server may be improved by utilizing computing resources on a client. Initial search results produced by the server search engine are further processed on the client machine, which may produce a more refined set of search results. The processing on the client machine may be done using a client-side search program. The usefulness of the search results to a user may therefore be improved without the need for additional server resources. Data associated with the additional search results produced by the processing on the client may be sent back to the server. The server may then update its search engine such that results for subsequent searches on the server may be improved. A system for implementing the improved searching may include a network server having a server-side search program and a network client having a browser and a client-side search program.

Abstract: An architecture, system and method are provided for efficiently transferring packets of data across a communication network. The communication network is structured such that there are hierarchical levels of high speed switches existing throughout the network. Distributed routing of packets is achieved by comparing identification numbers of only select switches with the destination address on a field-by-field basis. Not all fields need be compared at all switches. Once routing is achieved within the structured network, transfer to a destination termination device occurs through a single look-up table only when departing the network if multiple termination devices are present at that exit node. The routing operation between termination devices can therefore be achieved using a single mapping operation (if more than one termination device must be selected) and is backward compatible with devices external to the network and protocols used by those devices.

Abstract: A system and method are disclosed for a common set of Component Peer classes for the Java abstract windowing toolkit (AWT). The native methods employed by the various platform-specific versions of a Peer class are similar in operation, but contain differences in the source code of the C/C++ functions that implement them. Consequently, they represent distinct bodies of software, which must be supported and maintained separately. The present invention provides a basis for replacing the diverse versions of the Component Peers with a single set, employing a standardized set of native methods. This results in a unique codebase for the Component Peers, across all the supported operating systems, thereby reducing the effort required to maintain and upgrade the software.

Abstract: A microelectromechanical device is provided which includes a contact structure interposed between a pair of electrodes arranged beneath a beam. In some embodiments, the device may include additional contact structures interposed between the pair of electrodes. For example, the device may include at least three contact structures between the pair of electrodes. In some embodiments, the beam may be suspended above the pair of electrodes by a support structure affixed to a first end of the beam. Such a device may further include an additional support structure affixed to a second end of the beam. In some cases, the device may be adapted to pass a signal from the first end to the second end of the beam. In addition or alternatively, the device may be adapted to pass the signal between one or both ends of the beam and one or more of the contact structures.

Abstract: A CMP system, a wafer carrier, and components of a wafer carrier are provided for processing a semiconductor topography. In particular, a CMP system, a wafer carrier, and components of a wafer carrier are provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the semiconductor topography may include any region of the topography. The wafer carrier components may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of the semiconductor topography than in a second portion of the semiconductor topography.

Abstract: A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract: An improved clock generation circuit using a multi-phase phase-locked loop (PLL) circuit design that incorporates a dual set of PLLs. A first PLL maintains frequency lock control of an oscillator while a second PLL controls various phase outputs from delay circuits external to the oscillator which are locked in time delay with phase outputs from the oscillator. In this fashion, 2N phase outputs can be achieved with an oscillator that only produces N phase outputs. Furthermore, the second PLL uses a three-input phase detector that compares the phase output from one of the delay circuits external to the oscillator with a pair of phase outputs from the oscillator. Depending on the timing relationship of those output phases, the three-input phase detector will yield either a predominant pump-up pulse or a predominant pump-down pulse, through which the second PLL will use these signals to control the phase output of the external delay circuits relative to the phase outputs from the oscillator.

Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.

Abstract: A memory circuit which is adapted to identify memory cells within a first time interval for a write operation of the circuit and identify the memory cells within a second time interval for a read operation of the circuit is provided. In some cases, the memory circuit may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. In addition, the memory circuit may include a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the memory circuit may further include a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the memory circuit may be absent a means for intentionally delaying the identification of memory cells for the read operation of the circuit.

Abstract: A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/−2&pgr;. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.

Abstract: A circuit, system, and method are provided for regulating the mark-to-space ratio of a clocking signal. In instances where the mark-to-space ratio is targeted at 1:1 (i.e., a 50% duty cycle), then a regulated signal is formed which will produce a 50% duty cycle whenever that regulated signal is forwarded to a buffer which will produce a duty cycle other than 50% if the input signal were not regulated. The regulated signal is derived from a feedback circuit which will take into account the periodic nature of the clocking signal and whatever threshold skews might be attributable to the clock buffer. The feedback signal derives its input from a tap connected to receive the clocking signal from an output of the buffer, and the tap forwards that clocking signal to switching transistors which impute the periodic clocking frequency onto a threshold skewed output which will then form the regulated signal. Any skew resulting from the oscillator will not be passed to the node which bears the regulated signal.

Abstract: An improved communication system, receiver, and method are provided that can reduce input voltages received by the receiver whenever those voltages extend upward to the maximum common-mode voltage range. A detect circuit determines whether the input voltages are at or near the maximum range. If so, the detect circuit sends a control signal to a level shift circuit which will reduce the input voltages by a predefined amount. The reduced voltages can then be forwarded to a sense circuit which preferably operates at a power supply voltage that is less than the maximum differential input voltage (i.e., the maximum voltage on the differential pair of signals), or less than the maximum common-mode voltage of the differential input signals. The sense circuit can thereby operate at a relatively wide common-mode voltage range, and utilizes a lower power supply voltage.

Abstract: A communication system is provided for interconnecting a network of digital systems. The communication system includes a communication line and a transceiver placed between the communication line and each digital system. The transceiver includes a receiver which can be selectively powered down whenever activity within the communication line ceases. The external conductors extending from each transceiver integrated circuit to an associated digital system are minimal, and the status of a clock/status signal conductor will indicate if the digital system is in a low power state (no clocking signal) or whether the digital system will be in a normal or protected clocking state. When a communication system is initially started, activity within the communication line will not lock the recovery circuits of the transceiver and, therefore, the transceiver will forward the received signal back out the transceiver without causing that signal to enter the associated digital system.

Abstract: A method is provided for processing a semiconductor topography. In an embodiment, the method includes positioning a semiconductor topography against a carrier plate with a raised section. Such a method preferably allows a larger area capable of producing a target yield of semiconductor devices within dimensional specifications to be obtained than is obtained by positioning the topography against a carrier plate with a flat surface. As such, positioning a topography against a carrier plate with one or more raised sections may form a substantially planar upper surface in a larger area than in an area formed by positioning such a topography against a flat surface carrier plate. Furthermore, such a method is preferably conducted in a single polishing step. As such, a polishing system is provided which includes a carrier plate with a raised section adapted to planarize a semiconductor topography in one polishing step.

Abstract: A circuit, system, and method is provided for regulating the pulse width and/or duty cycle of a signal indirectly or directly used to drive, e.g., a transmitter. The load of the transmitter can be, for example, an optical signal transmitter. The circuit includes a feedback loop that adjusts the output signal so that the lower voltages are chopped at a reference voltage input into the driver. The magnitude of the reference voltage will regulate the pulse width of the output signal, as well as the duty cycle of the output signal. A low input voltage swing is well-suited to be operated upon by the driver circuit to produce a symmetric pulse width that is particularly adapted to high-speed optical data communication applications. The gain and slew rate of the feedback circuit and, predominantly, the comparator and pull-down transistor of the feedback circuit is tuned to ensure the pull-down transistor is always on and, therefore, the comparator will toggle, but within constrained (i.e., regulated) voltage limits.

Abstract: A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.

Abstract: Architectures, systems, and methods are provided for securing and prioritizing packets of data sent through a communication network. Each packet is assigned a security code and priority code as it enters the network. The security code or priority code may remain the same or change as it travels from node-to-node across the network. By assigning security and priority codes to each packet, maximum bandwidth allocation can be achieved among the nodes in a packet-switched environment. The assigned security and priority codes enter and travel through the network according to modules which have a hierarchical class or grouping. Thus, the security and priority information may be sent solely within one class or among classes depending on where, within the classes the data path exists.