Abstract: In a system and method for displaying status of critical indicators or variables, icons representing the indicators are displayed in superposition with a reference shape. The reference shape is divided into “higher-interest” and “lower-interest” portions, such that display of an icon over the higher-interest portion of the reference shape indicates a higher-interest value of the corresponding variable. The reference shape is preferably elongated horizontally, with its upper portion designated as the higher-interest portion and its lower portion designated the lower-interest portion. Each monitored variable may be allocated a vertical “slice” of the reference shape, such that the position of the corresponding icon when the variable is in the higher-interest state is laterally aligned with the position of the icon when the variable is in the lower-interest state.

Abstract: A method for configuring computer-based information for display includes assigning labels to information units stored in a computer system. The labels are used in grouping the information units. This grouping, performed by a user of the computer system, may result in group arrangements which can be accessed by a display controller associated with the computer system. A method for processing configuration information for display of computer-based information includes receiving input of a group arrangement, and storing the received group arrangement in data structures or rules databases. A method for displaying computer-based information includes detecting an instruction to display an information unit, identifying a group arrangement associated with the information unit, and forwarding the information units within the group to a display device.

Abstract: A fluid flow controller and method of operation thereof are presented. The fluid flow controller may include a casing having a casing blade. The fluid flow controller may also include a rotor having a first rotor blade and a second rotor blade radially spaced from the first rotor blade. The rotor may be configured to rotate relative to, and preferably within, the casing such that the casing blade passes between the first and second rotor blades during use. Compared to conventional pumps or compressors, the present fluid flow controller may have an enhanced ability to accelerate (and possibly to subsequently pressurize) fluid flow. Thus, the need to use multiple stages may be reduced or eliminated.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. In addition, the method may include forming channel dopant regions within the wells of opposite conductivity type. The formation of such channel dopant regions may be incorporated into the method using the one or two patterned layers used for the formation of the wells and doped silicon layer. Such a method may include introducing impurities at varying energies and doses to compensate for the introduction of subsequent impurities. As such, the method may form a dual gate transistor pair, including n-channel and p-channel transistors.

Abstract: In a system, method and program for monitoring and control of a circuit having a circuit breaker, circuit profile information characterizing the circuit is used to determine a reset strategy for resetting of the circuit breaker when it becomes tripped. The circuit profile information may include an identification of any devices connected along the circuit, and may further include device profile information characterizing such devices. An embodiment of the method includes detecting that the circuit breaker has tripped, receiving device profile information from a device connected along the circuit, using the device profile information to formulate a reset strategy for the circuit breaker, and sending a command as part of implementing the reset strategy. An embodiment of the system includes a system controller operably coupled to the circuit and the circuit breaker, where the system controller is adapted to use circuit profile information to determine a reset strategy.

Abstract: A method for communication with addressable, electronically-controllable appliances using a generalized pointing device is presented. The pointing device can communicate with dissimilar types of target appliance, and each appliance is associated with an appliance interface that makes the target appliance compatible with the pointing device. Use of the method is believed to allow the convenience associated with the use of a computer's graphical user interface to be realized in communication with physical objects, i.e. the target appliances. The method includes orienting the pointing device for reception of its pointer command signals by an appliance interface of the targeted appliance, transmitting a selection signal from the pointing device to the appliance interface, and transmitting a pointer command signal to the appliance interface.

Abstract: An embodiment of an amplifier circuit including a power supply node and an output node is adapted to provide, during operation, an output node voltage ranging to within 0.2 volts of a power supply voltage used during the operation. An embodiment of the circuit includes a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. In a method of providing an output voltage near the power supply voltage of an amplifier, a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage is produced. The first stage output voltage may further be coupled to a second stage of the amplifier, where the coupling may modulate a current flow through a first pair of cascaded transistors. An output node of the amplifier may be arranged between the pair of transistors and the power supply voltage node.

Abstract: A method of directing communication between addressable, electronically-controllable appliances using a generalized pointing device is provided. The pointing device can communicate with dissimilar types of target appliance, and each appliance is associated with an appliance interface that makes the target appliance compatible with the pointing device. Use of the method to direct communication between appliances is believed to allow the convenience associated with the use of a computer's graphical user interface (GUI) to be realized in communication with physical objects, i.e., the target appliances. In particular, the “drag-and-drop” method of using a GUI may be analogous to the pointer-mediated interaction between appliances provided herein.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.

Abstract: A method of configuring information for display includes assigning continuum labels to pieces of information, or information units, accessible by a computer system. The continuum labels may be used in arranging the information units into ordered sequences, or continuum arrangements. The method may include using a graphical user interface to establish sequences of icons representing information units. Forming continuum arrangements to configure information may allow display of the information in a form allowing rapid, convenient viewer access to desired pieces of information. In a method of displaying information, three axes are configured on a display screen, and selectable regions are configured in the vicinity of the axes, where each selectable region corresponds to an information unit. The position of the selectable region corresponding to an information unit is determined by a set of coordinates corresponding to x-axis, y-axis and z-axis continuum labels assigned to the information unit.

Abstract: A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

Abstract: Systems and methods for presenting (e.g., displaying) a hierarchical structure are presented. The hierarchical structure includes multiple elements and defines hierarchical relationships between the elements. The hierarchical structure may be embodied within an electronic document such as a Web document, an interactive application program, or a map divided into sections. Each element has a “presentation property” which may be a value or a function. One of the elements has “focus” (e.g., as created, by default, etc.). A “branch isolation” method includes forming a tree-like model of the hierarchical structure having multiple nodes and at least one branch. Each node represents one of the elements. One node is a root node and occupies a highest level in the hierarchical structure. A given branch connects a first node in a first level to a second node in a level directly below the first level. Each branch represents a hierarchical relationship between connected nodes.

Abstract: An adsorbent gas scrubber is provided in which the processing efficiency of the gas generated during semiconductor manufacturing can be increased, as the idle time of the system is reduced. The above mentioned object and other objects are accomplished by an adsorbent gas scrubber in accordance with aspects of the present invention which comprise an induction tube being connected to a gas inlet attached with a first pressure gauge for measuring a pressure of the entered gas, and an adsorbent case placed adjacent to the induction tube. The adsorbent case contains a layered arrangement of multiple catalytic-adsorbent members which adsorb the gas that flows from the induction tube to a gas outlet attached with a second pressure gauge for measuring pressure of the processed gas being discharged. A series of gas passage tubes placed at the bottom portion of the induction tube and the adsorbent case supply gas to the catalytic-adsorbent members.

Abstract: A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared.

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: The present invention advantageously provides a method for retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent processing steps. According to an embodiment, alignment marks are etched into a semiconductor substrate. Thereafter, a pad oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. Isolation trenches which are deeper than the alignment mark trenches are formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A substantially transparent dielectric, e.g., oxide, is then deposited across the semiconductor topography to a level spaced above the first nitride layer.

Abstract: An embodiment of a memory cell includes a series of four substantially oblong parallel active regions, arranged side-by-side such that the inner active regions of the series include source/drain regions for p-channel transistors, and the outer active regions include source/drain regions for n-channel transistors. Another embodiment of the memory cell includes six transistors having gates substantially parallel to one another, where three of the gates are arranged along a first axis and the other three gates are arranged along a second axis parallel to the first axis. In another embodiment, the memory cell may include substantially oblong active regions arranged substantially in parallel with one another, with substantially oblong local interconnects arranged above and substantially perpendicular to the active regions.

Abstract: A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.

Abstract: A method, system, and storage medium for determining retide tilt in a lithographic system is provided. Test patterns contained on a reticle are printed in a photoresist located on an upper surface of a semiconductor substrate by a lithographic system. The test patterns may include three posts of different diameters wherein one of the diameters is approximately equal to the minimum allowable feature size printable by the lithographic system. Images of the test patterns are measured by a scanning electron microscope under the control of a computer system. The computer system then assesses the measured images of the test patterns to determine if the reticle tilt is acceptable or unacceptable. In one embodiment, the computer system may assess the measured images by comparing the measured images to predetermined images of the test patterns for different focus conditions. The computer system may also calculate the amount of reticle tilt.