Abstract: A method of configuring information for display includes assigning continuum labels to pieces of information, or information units, accessible by a computer system. The continuum labels may be used in arranging the information units into ordered sequences, or continuum arrangements. The method may include using a graphical user interface to establish sequences of icons representing information units. Forming continuum arrangements to configure information may allow display of the information in a form allowing rapid, convenient viewer access to desired pieces of information. In a method of displaying information, three axes are configured on a display screen, and selectable regions are configured in the vicinity of the axes, where each selectable region corresponds to an information unit. The position of the selectable region corresponding to an information unit is determined by a set of coordinates corresponding to x-axis, y-axis and z-axis continuum labels assigned to the information unit.

Abstract: A network is described including a server and a network device remotely coupled to the server. The network device includes a non-volatile storage device having data stored therein, which is preferably modified solely in response to instructions generated by the server. During initialization, the network device performs a first portion of an operating system boot sequence then generates and forwards trigger data, which includes identification information for identifying the network device, to the server. In response, the server generates action data, which includes one or more data update instructions for modifying the data stored within the non-volatile storage device. Following a second portion of the operating system boot sequence, the action data is forwarded from the server to the network device. If the action data includes one or more data update instructions, the network device performs the one or more data update instructions and repeats the operating system boot sequence.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: An electronic document delivery system is described including a client machine coupled to (i.e., in wired or wireless communication with) a transcoder proxy. The client machine may be, for example, a palmtop or handheld computer or a wireless communication device with limited memory and/or processing capability. The client machine includes a Braille display and provides Braille format information identifying a selected Braille format to the transcoder proxy. The transcoder proxy is coupled to receive the Braille format information and electronic documents. Each electronic document includes presentation information (e.g., text and/or user controls such as buttons). The transcoder proxy includes a rule set including rules for translating electronic documents from any one of a set of first digital formats (e.g., a text-based markup language such as HTML, extensible markup language/XML, POSTSCRIPT, or portable document format/PDF) to any one of various Braille formats (e.g.

Abstract: A semiconductor device that includes an integrated circuit and an HBM structure formed on different semiconductor substrates is provided. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit and protection structures coupled to the input or output or input/output circuitry. In an embodiment, the integrated circuit may include input or output or input/output structures spaced across an area of the integrated circuit. The input or output or input/output circuitry of the HBM structure may be coupled to the input or output or input/output structures of the integrated circuit. A method for developing a design for an HBM structure is also provided. The method may include coupling an HBM structure formed on a first semiconductor substrate to an integrated circuit formed on a second semiconductor substrate. The method may also include testing the HBM structure and altering the HBM design based on the testing.

Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.

Abstract: An improved signaling system and method are provided that uses transconductance signaling rather than voltage or current signaling. A transient voltage applied to a first end of a conductor can produce a varying current placed into a low impedance node at a second end of the conductor. The second end is preferably pinned to a fixed voltage value, and the low impedance second end will allow current upon the second end to freely transition, enabling the conductor to arrive at a steady state condition much sooner than with conventional signaling methods. The present transconductance signaling method avoids large changes in voltage along the greater part of the conductor due to a current sent through this resistive conductor. This greatly improves transient behavior as, for example, evidenced by signal rise and fall times for digital signals produced by this transconductance signaling method.

Abstract: Several embodiments of an electronic document delivery system are described including a client machine (e.g., a palmtop/handheld computer or wireless communication device) coupled to a transcoder proxy. The system allows a client machine with limited resources to provide an assistive technology solution for a physically challenged user. In one embodiment, the client machine includes an assistive technology which functions as an interface for a device (e.g., a Braille display or a speech engine). The transcoder proxy receives an electronic document expressed in a first digital format (e.g., HTML or XML). The transcoder proxy assigns a unique identifier to the element, and forms a model of a logical structure of the document (e.g., a document object model or DOM). The transcoder proxy uses the model to produce an “original” script including a portion of the document expressed in a second digital format (e.g., a scripting language).

Abstract: Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch.

Abstract: A method and processor configured to handle an exception may employ a “retry” signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one embodiment for which the exception is an interrupt, the retry signal is asserted when memory access is delayed and the processor may proceed to service an interrupt request during this period of delayed memory access, regardless of the degree of completion of an instruction by the processor. During a period of delayed memory access, the processor may suspend instruction execution until the memory access becomes available. Upon completion of servicing the interrupt, the processor may resume instruction execution beginning with the last instruction attempted before the suspension of the instruction execution due to the delayed memory access.

Abstract: In a method for forming a micromechanical device, a force associated with operation of the device is varied between locations spaced across a conductive element of the device. The method may be used to form a switch adapted such that a force associated with actuation of the switch varies between locations spaced across a contact element of the switch. The varied force may include a required closing force for the switch, an applied force during actuation of the switch, a restoring force tending to open the switch, and/or a sticking force tending to keep the switch closed. A variable-valued circuit element having a conductive element and conductive pad may also be formed, adapted such that a fraction of the conductive element which is moved to the proximity of the conductive pad is variable depending on a total magnitude of a force applied.

Abstract: A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency.

Abstract: A deserializer within, for example, a transceiver is provided having multiple stages of pipelined demultiplexers. Each demultiplexer within the earlier stages of the pipelined architecture use only three latches. Two latches are dedicated to producing an odd bitstream (or even bitstream) from odd and even bits within the incoming serial bitstream. Another latch is dedicated to producing an even bitstream (or odd bitstream) from even and odd bits of the serial bitstream. Using only three latches within early stages of the pipelined architecture reduces power consumption and overall size of the deserializer. Clocking signal frequencies of subsequent stages are reduced and the clocking signals are delayed in order to align data outputs from the previous stage with transitions of clocking signals forwarded to the respective stages.

Abstract: A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including CxHyFz, in which x≧2, y≧2, and z≧2 is provided. Such an etch chemistry may be selective to the barrier layer. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, critical dimensions of contact openings formed with such an etch chemistry may be uniform from wafer to wafer.

Abstract: The invention provides a method and system for lookup (such as for example, lookup of message header information) that records information in a relatively large database in a relatively compact structure, while still providing for relatively rapid lookup and update. A relatively large but compact database includes a hybrid tree (or hybrid trie) structure, whereby information in denser portions of the database can be stored and retrieved from an identifiable leaf in the hybrid trie. The hybrid trie includes at least one leaf node marked to include a different data structure, whereby information in sparser portions of the database can be stored and retrieved from a more densely packed table.

Abstract: A circuit and method are disclosed herein for a multi-phase voltage-controlled LC oscillator. The oscillator is configured as a ring containing N sections, each of which has an LC tank circuit that determiines the oscillation frequency. All the oscillator sections produce a signal at the same frequency, but with a constant phase angle offset between one section and the next. Thus, for example, a 4-phase version of the oscillator would have 4 sections, producing signals with phase angles of 0°, 90°, 180°, and 270°. The phase offset in each section results from the use of amplified quadrature signals to drive the LC circuits. An advantage of this approach to obtaining multiple phases is enhanced frequency stability, since the LC circuits in the oscillator sections all operate at resonance. Frequency modulation is accomplished without the use of varactors or other voltage-controlled tuning devices.

Abstract: An improved wafer clamp retainer is provided. The retainer is used to movably secure a wafer clamp to an upper electrode within a parallel-plate reactor. When drawn downward, the wafer clamp is pressed by the retainer against an outer periphery of the wafer to hold the wafer against the lower electrode. When drawn upward, the retainer lifts the wafer clamp from the wafer so that the wafer can be accessed. The wafer clamp retainer includes one or more features formed about an outer surface of a shaft extending from one end of the retainer body. The feature can comprise one or more rings, or spiral threads which mate with a flexible washer. The washer can be pushed directly upon the shaft and snap-fitted with the features or, alternatively, threaded upon the shaft by employing mating features on the wall which surrounds the opening through the washer.

Abstract: A clock may be combined with an asynchronous RAM to create an asynchronous RAM that works within a subset of a full clock period, but allows the address access and other internal RAM functions to occur throughout the clock period. The present invention simplifies the timing analysis of the logic path through the RAM, increases the clock frequency of the resulting logic (compared to a synchronous RAM with narrow timing window), reduces the current requirements (compared to asynchronous RAM), and allows the combinatorial logic to be changed late in the design cycle without the need for a RAM redesign. As more and more logic is synthesized and internal RAM is used to put increasing function on the same die, the structure of the present invention meshes well with synchronous synthesized logic design methodologies, while at the same time recognizes the need to be as stingy as possible with operating current.

Abstract: A circuit is provided herein, which is adapted to supply different current magnitudes along opposing directions of a conductive line. Such a circuit may be particularly beneficial in compensating for the effects of unintentional magnetic coupling within MRAM devices. In addition, a method is provided herein for configuring a device having a magnetic memory array, which receives a first current magnitude along one direction and a substantially different current magnitude along an opposite direction of the magnetic memory array. Furthermore, a method is provided herein which assigns tunable current magnitudes for write operations along conductive lines of a memory circuit. Such tunable writing currents advantageously increase the write selectivity of the memory circuit. More specifically, the tunable writing currents compensate for ferromagnetic and antiferromagnetic coupling within magnetic memory cells caused by uneven surface topology and non-zero total magnetic moments, respectively.

Abstract: A method is provided, which includes patterning a stack of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include patterning a lower hardmask layer arranged above the stack of layers. Such a patterning process may include removing the entire sacrificial hardmask layer. For example, the method may include patterning an upper portion of the stack of layers using the sacrificial hardmask layer as a first mask and patterning a lower portion of the stack of layers using the lower hardmask layer as a second mask. Consequently, a semiconductor topography is provided herein which includes a sacrificial hardmask layer arranged above a plurality of layers. Such a sacrificial hardmask layer may include a material with substantially different etch characteristics than one or more upper layers of the plurality of layers and substantially similar etch characteristics as one or more lower layers of the plurality of layers.