Abstract: A computer is disclosed having a power supply assembly that may be rotated into a first position for operating the computer, rotated into a second position for servicing components within the computer, or removed from the computer quickly and easily. The power supply assembly is mounted to a chassis via first and second pivot pins that define an axis of rotation and engage first and second bearing surfaces. The first pivot pin may be disengaged from the first bearing surface without removing a fastener. In one embodinent, the first pivot pin is disengaged from the first bearing surface by relative movement between the first pivot pin and the first bearing surface along the axis of rotation. In another embodiment, the first pivot pin is disengaged from the first bearing surface by passing it through a slot in the bearing surface orthogonal to the axis of rotation.

Abstract: A heatsink for use with an actively cooled daughterboard system. Plural transverse fins are integrally formed with a base portion. The fins are parallel to one another and orthogonal to the bottom of the base portion. The fins have a constant profile relative to the bottom of the base portion, but the base portion has a central portion that is thicker than its end portions. The thickness of the central portion varies according to a radius. The radius is approximated by step differences in the depths of the fins.

Abstract: A two-piece bus bar electrically couples a printed circuit board to a power supply. The power supply is mounted to a chassis. A power supply bus bar extends from the power supply, defining a power supply bus bar plane. A first printed circuit board is mounted to the chassis and oriented in a plane that is not parallel with the power supply bus bar plane. A first printed circuit board bus bar extends from the first printed circuit board. At least one of the power supply bus bar or the first printed circuit board bus bar includes a bend that creates a parallel relationship between a mating portion of the power supply bus bar and a mating portion of the first printed circuit board bus bar. A first fastener couples the mating portions of the bus bars together. A second printed circuit board may be mounted to the chassis and oriented in a plane at right angles with the power supply bus bar plane.

Abstract: Two opposing connector catches are disposed on resilient stems at the bottom of a circuit board retainer. A frame is disposed between the catches. The frame fits around the profile of a connector. The catches slip over the ends of the connector and engage shoulders on the ends of the connector. Opposing upright members are coupled to the frame and the catches. A circuit board is lowered between the upright members. Two opposing board catches on the upright members engage corresponding notches formed in the circuit board. To disassemble the circuit board from the retainer, the upright members are bent away from one another to disengage the board catches from the notches. To disassemble the retainer from the connector, the upright members are bent toward one another to disengage the connector catches from the shoulders.

Abstract: A hinging cable management arm is disposed inside a rack behind a slidingly mounted computer. The arm folds and unfolds as the computer slides into and out of the rack. Cables from the computer are secured to the arm with cable ties. The arm includes two elongate members hingingly coupled to one another at one end. At the other end, one member is hingingly coupled to the rack and one member is hingingly coupled to a sliding computer mount. Each elongate member has a u-shaped profile. The hinged couplings are implemented using swaged pins. The cable ties are straps made with hook-and-loop fabric. The straps are made captive to the elongate members by anchoring them at a first slot and threading them through a second slot. They are wrapped over the computer cables and around the profile of the elongate members until the hook-and-loop material secures to itself.

Abstract: A one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common storage system, and demultiplexer and control circuitry. The demultiplexer and control circuitry are configured so that cycle information destined for the first I/O bus interface is enqueued from the system bus interface into the first logical FIFO and is dequeued from the first logical FIFO into the first I/O bus interface. Cycle information destined for the second I/O bus interface is enqueued from the system bus interface into the second logical FIFO and is dequeued from the second logical FIFO into the second I/O bus interface. A level-of-fullness monitor monitors the common storage system and generates first and second level-of-fullness indications responsive thereto. The system bus interface is operable to declare I/O halt and I/O resume conditions on a system bus responsive to halt and resume commands.

Abstract: An actively cooled daughterboard system. One more daughterboards are mounted in parallel rows on a motherboard. Each daughterboard is oriented substantially perpendicular to the motherboard, but may optionally be mounted at an oblique angle relative to the motherboard. Each daughterboard has a low-profile thermally-efficient heatsink mounted thereon. A fan shroud partially covers the daughterboards, but has openings in its sides for directing air flow through plural fins on the heatsinks and through a fan mounted to the top of the fan shroud. The inventive daughterboard system enables multiple high heat dissipating daughterboards to be placed closer together than the daughterboard systems of the prior art while still keeping the daughterboards adequately cooled. Moreover, because only a single fan is used to cool all of the daughterboards under the shroud, noise and expense are reduced relative to prior art systems that employed one or more fans per daughterboard.

Abstract: A heatsink for use with an actively cooled daughterboard system. Plural transverse fins are integrally formed with a base portion. The fins are radially displaced from one another. The base portion includes a central portion that is thicker than the end portions. The thickness of the base portion and the profile formed by the outer ends of the fins vary according to radii. The inner radius associated with the central fins is shorter than the inner radius associated with the endmost fins.

Abstract: A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. In a first embodiment, the free register identifier is implemented using a priority encoder. In a second embodiment, the free register identifier is implemented using a conventional FIFO buffer. In a third embodiment, the free register identifier is implemented using one of the logical FIFO buffers stored in the main register file.

Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data.

Abstract: A single logical screen computer display uses multiple remote computer systems operable to perform hardware accelerated 3D graphics operations. The display system includes a client process, a first slave host computer coupled to first display hardware, a second slave host computer coupled to second display hardware, and a network broadcast path between the client process and the first and second slave host computers. The client process is operable to broadcast OGL command buffers to the first and second slave host computers using the network broadcast path. The first and second slave host computers are operable to execute OGL commands in the OGL command buffers and to render the results on the first and second display hardware, respectively. First and second X server processes run on the first and second slave hosts, and first and second OGL daemon processes also run on the first and second slave hosts.

Abstract: A compressed texture data structure is disclosed. The structure includes at least first and second compressed texture data segments. The first compressed texture data segment starts at a first segment starting memory location, ends at a first segment ending memory location, has a first segment length, and contains a first compressed texture data block having a first compressed texture data block length. The second compressed texture data segment starts at a second segment starting memory location, ends at a second segment ending memory location, has a second segment length, and contains a second compressed texture data block having a second compressed texture data block length. The first and second compressed texture data blocks contain compressed representations of first and second uncompressed blocks of an uncompressed texture map. The second segment starting memory location is disposed contiguously with the first segment ending memory location.

Abstract: A method for handling events in an X Window System environment is disclosed. First and second events are detected in first and second server processes, respectively. First event data corresponding to the first event is stored in a first event cache associated with the first server process. Second event data corresponding to the second event is stored in a second event cache associated with the second server process. The first and second server processes are polled to determine whether they have detected any events. If it is determined that both the first and second server processes have detected events, the first and second event data is requeted from the first and second server processes. The first and second event data is coalesced into coalesced event data. The coalesced event data is delivered to a client process.

Abstract: Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. In one embodiment, a hierarchical one of the plural primary nodes includes plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line. In another embodiment, a hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line.

Abstract: Synchronization of frame buffer swapping among computer graphics pipelines in a multi-pipeline display system: The pipelines are arranged in a closed daisy chain loop. One pipeline is configured as master; the others are configured as slaves. The master swaps its frame buffers and propagates a master swap signal through the daisy chain. As each slave recognizes the signal, it swaps its own buffers. Each slave propagates a feedback signal back to the master to indicate whether the slave is ready to swap its buffers again. The master waits until the feedback signal indicates that all slaves are ready to swap their buffers before the master will swap its own buffers a second time. The process repeats when the master swaps its buffers a second time.A first synchronization control system is coupled to a first pipeline and has a first daisy chain input and a first daisy chain output.

Abstract: A method for retrieving compressed texture data from a memory system while conserving bus bandwidth and memory bandwidth is disclosed. The method is particularly useful when the compressed texture data sought to be retrieved is stored in memory in the form of blocks that have varying lengths. A starting address is determined for a target compressed texture data segment stored in the memory. The target compressed segment contains a compressed data block which in turn contains a compressed representation of the texture data sought to be retrieved. A read request issuance operation is commenced, beginning with the starting address of the target segment. Various techniques are disclosed for stopping the read request issuance operation once it is determined that sufficient read requests have been issued to retrieve a complete compressed representation of the texture data of interest.

Abstract: Integral hem rivets fasten a front end panel, a back end panel and internal structural support members to a main sheet metal panel of a computer enclosure. The main sheet metal panel forms a cosmetic surface for the computer enclosure. The integral hem rivets used to fasten pieces to the main sheet metal panel do not blemish the cosmetic surface. In addition, the configuration of the hem conserves volume within the enclosure for mounting internal system components.

Abstract: Method and apparatus for synchronizing vertical refresh and the display of left versus right channels in a stereoscopic, multi-display computer graphics system. Each graphics pipeline in the system is coupled to its own synchronization controller. The synchronization controllers each have a synchronization input and a synchronization output. The inputs and outputs are coupled in series to form a daisy chain. One of the synchronization controllers is designated the master, the rest are slaves. The master generates a signal that transitions when the master enters vertical front porch. The slaves pass this signal down the daisy chain. Each slave will wait at the end of its own vertical front porch for a transition on the signal. When the transition occurs, the slave immediately enters vertical sync. If no transition occurs within a predetermined time, the slave will enter vertical sync at the end of the predetermined time.

Abstract: A mounting system for facilitating removal and replacement of circuit cards in a card cage includes a carrier having a generally planar shape and having a plurality of location holes therethrough. A first circuit card edge support is disposed at the bottom edge of the carrier. A first anchor assembly includes a first circuit card locator and a fastener system. The first circuit card locator is removably mounted to the carrier by the fastener system, a portion of which passes through one of the location holes in the carrier. The first circuit card locator is equipped with a support ledge and a hold-down tab for engaging opposite sides of a circuit card while the first circuit card edge support engages an edge of the circuit card. A second anchor assembly includes a post oriented generally perpendicular to the plane of the carrier and passes at least partially through a tooling hole in the circuit card. A second circuit card edge support may also be disposed at the bottom edge of the carrier.

Abstract: Printed circuit board has first, second and third sets of connection points operable to connects to first, second and third integrated circuits. Each set of connection points is arranged in a grid pattern having a center pairs of orthogonal axes intersect. The grids define parallel planes. The pairs of orthogonal axes of the second grid are rotated counterclockwise relative to those of the first grid by at least 5 but not more than 25 degrees. Signal connection points in the first and second grids are concentrated in corners closet to the center of the third grid. Signal connection points in the third grid are concentrated in the half closest to the centers of the first and second grids. Alternatively, when signal connection points are concentrated elsewhere in the grid, the pairs of axes for the second grid are rotated relative to those of the first by an amount other than 0, 45, 90, 135, 180, 225, 270 and 315 degrees. First and second sets of mounting holes attach first and second heat dissipators.