Abstract: A computer enclosure locking mechanism. A bracket is disposed near the edge of a first enclosure panel. The bracket includes a latchpin retaining surface and a standoff member. The first panel includes a first latchpin clearance hole. The standoff member includes a lock bar clearance hole for receiving the lockbar of a padlock or other locking device. A retractable latchpin having a longitudinal member and a head is provided. A spring is disposed coaxially around the longitudinal member. A second enclosure panel includes a second latchpin clearance hole that aligns with the first latchpin clearance hole when the first and second panels are brought together at a seam. When the latchpin is retracted, the head rests against the latchpin retaining surface and the longitudinal member extends through the first clearance hole but not through the second clearance hole, thereby enabling the first and second panels to be separated or brought together.

Abstract: A method and apparatus for transferring a block of pixel data from a source multi-line frame buffer area to a destination multi-line frame buffer area in a raster-type computer graphics display system. The method steps are performed by a state machine embedded in a macro function unit within a computer graphics subsystem: It is first determined whether the first raster line corresponding to the destination multi-line frame buffer area is at least a minimum number of raster lines ahead of the current raster line. If so, the state machine follows a fast path, during which the pixel data are transferred one line at a time from the source multi-line frame buffer area to the destination multi-line frame buffer area until the last line of pixel data in the block has been transferred. Then, the transfer operation stops. If not, then the state machine follows a slow path.

Abstract: A corner buffer system for improving memory read efficiency during the process of determining a bilinearly interpolated texel value corresponding to a pixel. The corner buffer system includes a conditional texel quad transposer, a conditional s,t fraction complementer and a corner buffer unit. Addresses for data words corresponding to each texel in a texel quad are received, as well as the two LSBs of the s,t coordinates for at least one of the four texels in the quad. The conditional texel quad transposer routes the texel addresses to first, second, third and fourth outputs according to the values of the LSBs of the s,t coordinates of each texel. The conditional s,t fraction complementer receives the fractional parts of the s,t coordinates of the pixel and conditionally complements them responsive to the state of the LSBs of the s,t coordinates of one of the four texels. The corner buffer unit has four address inputs and includes four sets of address storage registers and data storage registers.

Abstract: Two or more cross-triggering CPUs for enhancing test operations in a multi-CPU computer system. Method for using same. A first CPU has a first trigger input, a first trigger output and first internal test-facilitating circuitry operable to assert the first trigger output when a first event occurs within the first CPU, and also operable to take a first test-facilitating action response to an assertion of the first trigger input. A second CPU has a second trigger input, a second trigger output and second internal test-facilitating circuitry operable in the same way. The first trigger output is coupled to the second trigger input, and the second trigger output is coupled to the first trigger input. (The arrangement may be extended to include any number of CPUs.) The trigger input and trigger output in each CPU may both be coupled to a bidirectional chip pad in the CPU, and the bidirectional chip pads of each CPU coupled together.

Abstract: A probe plate assembly for use in a circuit board test fixture is disclosed. First and second plates are mounted substantially parallel to one another and with a space between them. Probe pins are mounted to the first plate and oriented so that they can contact a device under test on the side of the first plate opposite the space. Electrical contacts are mounted to the second plate and oriented so that they can contact a test head on the side of the second plate opposite the space. Flexible conductors electrically couple the probe pins to the electrical contacts. In a disclosed embodiment, the probe pins are spring probes, and the second plate contains clearance holes disposed adjacent the spring probes. Each of the clearance holes has sufficient diameter to allow the socket tail of one of the spring probes to pass through it without substantial friction. The result is that forces from the test head are mechanically decoupled from the first plate, thus preventing bowing of the first plate.

Abstract: Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information.

Abstract: A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to detect whether input data is primitive information or pass-through information. If it is the former, the information is processed as a primitive. If it is the latter, the hardware determines whether one of the dual-port RAMs is available. If so, the available RAM is converted into a pass-through FIFO, and the pass-through information is stored therein. An output process operates continually to send primitive results and pass-through information from the pass-through FIFO out of the graphics processor output as the information becomes available, and ensures that the correct ordering of the information is maintained. If necessary, and if both RAMs are available, both of the dual-port RAMs in the graphics processor may be used as pass-through FIFOs at the same time.

Abstract: A printed circuit spark gap for an overcoated printed circuit board. A metal-clad substrate is etched to form first and second printed circuit traces on the substrate. The first and second printed circuit traces define a channel having first and second ends. A layer of soldermask is deposited onto the substrate to cover a portion of the first and second printed circuit traces and to cover the channel except at an aperture. The aperture includes the spark gap. The first and second printed circuit traces and the channel are covered with a capping device. An overcoating material is applied to the printed circuit board. During the applying step, the overcoating material is allowed to infiltrate into the channel under the capping device at the first and second ends, but is not allowed to reach the aperture. Counter pressure buildup inside the channel, caused by the infiltration itself, stops the overcoating material before it reaches the intended clean area.

Abstract: An edge-testable circuit board includes a circuit board having a planar surface and a board edge. Conductive pads are formed on the board edge and are electrically coupled to test nodes of the circuit on the circuit board. The conductive pads may be located within indentations formed on the board edge. The indentations may be half-circles, half-squares or v-shaped. The conductive pads may be formed by making plated through-holes in the circuit board, electrically coupling the plated-through holes to test nodes on the circuit board, and then removing part of the plated-through holes with a router. The removal step creates a new board edge that exposes part of the plating of the through hole. Numerous such conductive pads may be formed in one step by centering the plated-through holes on a line and passing a router down the line. The circuit board may be tested by bringing it into contact with spring-loaded test probes mounted in a test fixture.

Abstract: An EMI gasket formed from a conductive sheet having a hole therein. A first set of conductive fingers is disposed along the periphery of the hole protruding away from the conductive sheet on the front side. A second set of conductive fingers is disposed along the periphery of the hole protruding away from the conductive sheet on the back side. The first conductive fingers are alternately interleaved with the second conductive fingers. Each of the first conductive fingers includes a first and a second portion defined by a bend. The first portion is disposed in the plane of the sheet. The second portion is disposed in a plane orthogonal to the plane of the sheet. The first conductive fingers operate to engage a conductive portion of a panel. The second conductive fingers operate to engage a conductive portion of a component. The conductive sheet and the first and second sets of conductive fingers are made of spring steel.

Abstract: Method and apparatus for controlling a computer bus having first and second bus slots and operable with a bus controller at first and second data transfer rates. When the computer bus is operating at the first data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled to the address/data pins of both of the first and second bus slots, and the control pins of the bus controller are coupled only to the control pins of the second bus slot. When the computer bus is operating at the second data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled only to the address/data pins of the first bus slot, and the control pins of the bus controller are coupled only to the control pins of the first bus slot. The second data transfer rate may be faster than the first data transfer rate.

Abstract: Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus.

Abstract: Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing.

Abstract: An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both.

Abstract: In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry.

Abstract: Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs.

Abstract: A method and apparatus are disclosed for determining the starting location and starting protocol of LAN data in a WAN frame. A list of offsets and a list of LAN protocols are maintained. For each offset in the offset list, the WAN frame is parsed beginning at the offset and each LAN protocol in the LAN protocol list is looked for, one at a time. If no LAN protocol is recognized to begin at this offset, the next offset in the offset list is chosen and all of the LAN protocols are tried once again beginning at the newly-chosen offset. This process is repeated until all of the LAN protocols are tried at all of the offsets, or until a LAN protocol is recognized. If a LAN protocol is recognized, the offset at which the protocol was recognized is reported, together with the identity of the LAN protocol that was recognized at the offset. If a LAN protocol is not recognized, an appropriate error message is reported.

Abstract: An enhanced test system in a processor having a memory supporting multiple memory schemes. The memory is partitioned into memory blocks and memory sub-blocks. A plurality of uniform data units each comprising a plurality of data fields is written to and read from each successive memory block in a FIFO manner so that a data field within each data unit, having a maximum field width, occupies each of the multiple memory locations at least once during testing. The enhanced test system maximizes the number of adjacent full-width data fields to test vertically and horizontally for field overflow within memory by writing and reading seriatim by data unit or partitioned by data field width, in adjacent memory blocks and sub-blocks, or overlapping memory blocks and overlapping sub-blocks.

Abstract: A non-linear digital-to-analog converter (non-linear "DAC") and method are disclosed for scaling a digital input value by a non-integer and producing an analog output. The digital input value is multiplied by a non-integer, and the integer portion of the result is fed to a linear DAC to produce a linear analog output. At least one of the bits of the integer portion of the result is decoded, and at least one compensation value is generated responsive to the decoding. The compensation value is added to the linear analog output and represents the fractional portion of the result of scaling the digital input value by the non-integer. A method is also disclosed for utilizing the non-linear DAC for error compensation in a computer graphics system. Color intensity values are scaled up by a non-integer greater than one. A first analog output is generated proportional to the integer portion of the result.

Abstract: An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption.