Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A semiconductor circuit array comprises a plurality of repetitive circuit blocks. Each of the circuit blocks comprises a plurality of functional circuit segments. Each of the functional circuit segments is physically oriented in on of a plurality of predetermined orientations independent of other functional circuit segment orientations in the circuit block.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract: A content addressable memory (CAM) including a plurality of rows, each of the rows has a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.

Abstract: A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method including the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segments each having a length of the predetermined operand size; multiplying a first segment value by a second segment value to generate a first product value; the second at least one of the segment values to derive a second product value; halving the second product value to generate a halved second product value; accumulating the first product value with the halved second product value to generate an accumulated value; and doubling the accumulated value to generate the intermediate result.

Abstract: A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an accumulatd sum to produce a carry and save values; a carry-lookahead adder for adding said carry and save values to produce a product value and a carry-out value; a general purpose adder for adding said carry-out and said product value to produce said final product.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit includes a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further includes a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.

Abstract: A content addressable memory (CAM) for generating intermediate search results in a search on a stored data word sequence. The CAM comprises a plurality of rows of CAM cells each for storing a data word in the data word sequence; a plurality of match lines each coupled to a corresponding row of CAM cells, each for generating a corresponding match line signal.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: A system for managing a fleet of vehicles, which system comprises a central controller; a local controller for each vehicle: including a wireless communication interface for communication with said central controller; a geo-location device located in said vehicle for providing current geo-location information of said vehicle to said local controller; an interface associated with said central controller for inputting fleet management requests to said central controller; and an output device associated with said central controller for presenting a fleet operator with geo-location specific information received from said local controller and in response to said fleet management requests.

Abstract: A dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising: at least N−1 bitline pairs, each bitline pair being divided into N−1 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form N−1 groups of sub-bitlines each for producing one of N−1 reference voltages; sense amplifiers coupled to each sub-bitline pair; N−1 sub-bitline pairs each having reference cells for selective coupling thereto; (N−2)(N−1) sub-bitline pairs each having generate cells for selective coupling thereto; and sub-bitline pairs being selectively connected in a group through switches such that: the sub-bitlines in the group are precharged to one of a plurality of voltages; one of the (

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A circuit selectively adjusts the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of the input pulse in accordance with a second control input. The input pulse width is adjusted in accordance with a difference between the delay of the leading edge and the delay of the trailing edge.

Abstract: A high gain printed loop antenna comprises a first and second loop arranged symmetrically about a feed network, wherein each of the loops include pairs of substantially parallel radiation sections which when excited in phase from the feed network improves the gain of the antenna. Each of the parallel radiation sections are joined by patch elements such that the width of the patch elements is greater than the width of other portions of the loop. Thus, the patch elements allow for an increased variance in the path of a surface current through the loop.

Abstract: A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell further comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.

Abstract: A system and method for use in a real time system and for processing a signal with a low signal-to-noise ratio (SNR). The system comprises a model for modeling an expected signal and a filter that uses the model for filtering the signal. The filter is used for generating a prediction of the signal and an error variance matrix. The system further comprises an adaptive element for modifying the error variance matrix such that the bandwidth of the filter is widened, wherein the filter behaves like an adaptive filter.